NATIONAL SEMICONDUCTOR MARKING TYPE Search Results

NATIONAL SEMICONDUCTOR MARKING CODE sot

Abstract: national marking code NATIONAL SEMICONDUCTOR MARKING CODE DEVICE MARKING CODE table sot-23 MARKING CODE ZA On semiconductor date Code dpak YEAR A national top marking codes national marking date code national marking code sot sot23 mark code KS
Contextual Info: Device Marking Conventions National Semiconductor marks devices sold in order to provide device identification and manufacturing traceablility information. The method of presenting the information marked on the device is dependent on the size of the device package

fct574

Abstract: national marking code 883b
Contextual Info: 54FCT574 Octal D-Type Flip-Flop with TRI-STATE Outputs General Description Features The ’FCT574 is an octal flip-flop with a buffered common Clock CP and a buffered common Output Enable (OE). The information presented to the D inputs is stored in the

Contextual Info: LP38500/2-ADJ 1.5A FlexCap Low Dropout Linear Regulator for 2.7V to 5.5V Inputs General Description Features National's FlexCap LDO's feature unique compensation that allows the use of any type of capacitor with no limits on minimum or maximum ESR. The LP38500/2 series of lowdropout linear regulators operates from a +2.7V to +5.5V input

Contextual Info: DM54LS273 DM74LS273 8-Bit Register with Clear General Description Features The ’LS273 is a high speed 8-bit register consisting of eight D-type flip-flops with a common Clock and an asynchronous active LOW Master Reset This device is supplied in a 20pin package featuring 0 3 inch row spacing

30028

Abstract: chang aluminum capacitor LP38501TSX-ADJ LP38503-ADJ LP38503TS-ADJ LP38503TSX-ADJ LP38501-ADJ LP38501TS-ADJ
Contextual Info: LP38501/3-ADJ 3A FlexCap Low Dropout Linear Regulator for 2.7V to 5.5V Inputs General Description Features National's FlexCap LDO's feature unique compensation that allows the use of any type of capacitor with no limits on minimum or maximum ESR. The LP38501/3 series of lowdropout linear regulators operates from a +2.7V to +5.5V input

Contextual Info: DM54LS273 DM74LS273 8-Bit Register with Clear General Description Features The ’LS273 is a high speed 8-bit register consisting of eight D-type flip-flops with a common Clock and an asynchronous active LOW Master Reset This device is supplied in a 20pin package featuring 0 3 inch row spacing

ACT374

Abstract: 54ACT534DM
Contextual Info: 54ACT534 Octal D Flip-Flop with TRI-STATE Outputs General Description The ’ACT534 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and TRI-STATE outputs for bus-oriented applications. A buffered Clock CP and Output Enable (OE) are common to all

M 9580

Abstract: 646B
Contextual Info: 54F 74F646  74F646B  54F 74F648 Octal Transceiver Register with TRI-STATE Outputs General Description Features These devices consist of bus transceiver circuits with TRISTATE D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the input bus

5962-8863901

Contextual Info: 54FCT573 Octal D-Type Latch with TRI-STATE Outputs General Description Features The ’FCT573 is an octal latch with buffered common Latch Enable LE and buffered common Output Enable (OE) inputs. This device is functionally identical to the ’FCT373 but has

ABT-273

Abstract: ABT273
Contextual Info: 54ABT273 Octal D-Type Flip-Flop General Description The ’ABT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.

Contextual Info: 54F 74F821 10-Bit D-Type Flip-Flop General Description Features The ’F821 is a 10-bit D-type flip-flop with TRI-STATE true outputs arranged in a broadside pinout The ’F821 is functionally and pin compatible with the AMD’s Am29821 Y Commercial Y TRI-STATE Outputs

Contextual Info: 54F 74F377 Octal D Flip-Flop with Clock Enable General Description Features The ’F377 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock CP input loads all flip-flops simultaneously when the Clock Enable (CE) is LOW

74F273

Contextual Info: 54F 74F273 Octal D Flip-Flop General Description Features The ’F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock CP and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously

MIL-STD-188-114A

Abstract: MIL-STD-188 MIL-STD-188-114
Contextual Info: DS1692/DS3692 TRI-STATE Differential Line Drivers General Description The DS1692/DS3692 are low power Schottky TTL line drivers electrically similar to the DS1691A/DS3691 but tested to meet the requirements of MIL-STD-188-114A see Application Note AN-216 . MIL-STD-188-114A type 1 driver specifications can be met by adding an external three resistor voltage divider to the output of the DS3692/1692. The DS3692/

LM837N

Contextual Info: LM837 Low Noise Quad Operational Amplifier General Description Features The LM837 is a quad operational amplifier designed for low noise, high speed and wide bandwidth performance. It has a new type of output stage which can drive a 600Ω load, making it ideal for almost all digital audio, graphic equalizer,

Contextual Info: 100351 Low Power Hex D Flip-Flop General Description Features The 100351 contains six D-type edge-triggered, master/ slave flip-flops with true and complement outputs, a pair of common Clock inputs CPa and CPb and common Master Reset (MR) input. Data enters a master when both CPa and

Contextual Info: 100351 Low Power Hex D Flip-Flop General Description Features The 100351 contains six D-type edge-triggered, master/ slave flip-flops with true and complement outputs, a pair of common Clock inputs CPa and CPb and common Master Reset (MR) input. Data enters a master when both CPa and

f573

Abstract: F373 54F573DM
Contextual Info: 54F 74F573 Octal D-Type Latch with TRI-STATE Outputs General Description Features The ’F573 is a high speed octal latch with buffered common Latch Enable LE and buffered common Output Enable (OE) inputs This device is functionally identical to the ’F373 but has

E27014

Contextual Info: 54AC377 • 54ACT377 Octal D Flip-Flop with Clock Enable General Description The ’AC/’ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW.

ecl 100131

Contextual Info: 100331 Low Power Triple D Flip-Flop General Description Features The 100331 contains three D-type, edge-triggered master/ slave flip-flops with true and complement outputs, a Common Clock CPC , and Master Set (MS) and Master Reset (MR) inputs. Each flip-flop has individual Clock (CPn), Direct

Contextual Info: 100341 Low Power 8-Bit Shift Register General Description Features The 100341 contains eight edge-triggered, D-type flip-flops with individual inputs Pn and outputs (Qn) for parallel operation, and with serial inputs (Dn) and steering logic for bidirectional shifting. The flip-flops accept input data a setup

5962-9153601vya

Contextual Info: 100331 Low Power Triple D Flip-Flop General Description Features The 100331 contains three D-type, edge-triggered master/ slave flip-flops with true and complement outputs, a Common Clock CPC , and Master Set (MS) and Master Reset (MR) inputs. Each flip-flop has individual Clock (CPn), Direct

48V electronic power steering

Contextual Info: 100341 Low Power 8-Bit Shift Register General Description Features The 100341 contains eight edge-triggered, D-type flip-flops with individual inputs Pn and outputs (Qn) for parallel operation, and with serial inputs (Dn) and steering logic for bidirectional shifting. The flip-flops accept input data a setup

30028

Abstract: LP38501-ADJ LP38501TS-ADJ LP38501TSX-ADJ LP38503-ADJ LP38503TS-ADJ LP38503TSX-ADJ
Contextual Info: LP38501/3-ADJ 3A FlexCap Low Dropout Linear Regulator for 2.7V to 5.5V Inputs General Description Features National's FlexCap LDO's feature unique compensation that allows the use of any type of capacitor with no limits on minimum or maximum ESR. The LP38501/3 series of lowdropout linear regulators operates from a +2.7V to +5.5V input