MV 42H Search Results

OT 239

Contextual Info: LM5064 www.ti.com SNVS718D – JUNE 2011 – REVISED OCTOBER 2012 LM5064 Negative Voltage System Power Management and Protection IC with PMBus Check for Samples: LM5064 FEATURES 1 • • 2 • • • • • • • Input voltage range: -10V to -80V Programmable 26 mV or 50 mV current limit

88MC200 Microcontroller Datasheet

Abstract: 88MC200 software
Contextual Info: Marvell 88MC200 Microcontroller Datasheet Doc. No. MV-S108780-U0 Rev. B July 2013 Marvell. Moving Forward Faster Document Classification: Proprietary Information 88MC200 Microcontroller Datasheet Document Conventions Note: Provides related information or information of special importance.

Contextual Info: a +3 V, Dual, Serial Input Complete 12-Bit DAC AD8303 FUNCTIONAL BLOCK DIAGRAM FEATURES Complete Dual 12-Bit DAC Pretrimmed Internal Voltage Reference Single +3 V Operation 0.5 mV/Bit with 2.0475 V Full Scale Low Power: 9.6 mW 3-Wire Serial SPI Compatible Interface

Contextual Info: +3 V, Dual, Serial Input Complete 12-Bit DAC AD8303 a FEATURES Complete Dual 12-Bit DAC Pretrimmed Internal Voltage Reference Single +3 V Operation 0.5 mV/Bit with 2.0475 V Full Scale Low Power: 9.6 mW 3-Wire Serial SPI Compatible Interface Power Shutdown IDD < 1 ␮A

001H

Abstract: 800H AD8300 AD8303 AD8303AN AD8303AR
Contextual Info: a +3 V, Dual, Serial Input Complete 12-Bit DAC AD8303 FEATURES Complete Dual 12-Bit DAC Pretrimmed Internal Voltage Reference Single +3 V Operation 0.5 mV/Bit with 2.0475 V Full Scale Low Power: 9.6 mW 3-Wire Serial SPI Compatible Interface Power Shutdown IDD < 1 ␮A

2677006301

Contextual Info: BACK a +3 V, Dual, Serial Input Complete 12-Bit DAC AD8303 FEATURES Complete Dual 12-Bit DAC Pretrimmed Internal Voltage Reference Single +3 V Operation 0.5 mV/Bit with 2.0475 V Full Scale Low Power: 9.6 mW 3-Wire Serial SPI Compatible Interface Power Shutdown IDD < 1 ␮A

ladder diagram of AC servo motor

Abstract: ad8303j
Contextual Info: a +3 V, Dual, Serial Input Complete 12-Bit DAC AD8303 FEATURES Complete Dual 12-Bit DAC Pretrimmed Internal Voltage Reference Single +3 V Operation 0.5 mV/Bit with 2.0475 V Full Scale Low Power: 9.6 mW 3-Wire Serial SPI Compatible Interface Power Shutdown IDD < 1 ␮A

001H

Abstract: 800H AD8300 AD8303 AD8303AN AD8303AR AD8303-MC68HC11
Contextual Info: a +3 V, Dual, Serial Input Complete 12-Bit DAC AD8303 FEATURES Complete Dual 12-Bit DAC Pretrimmed Internal Voltage Reference Single +3 V Operation 0.5 mV/Bit with 2.0475 V Full Scale Low Power: 9.6 mW 3-Wire Serial SPI Compatible Interface Power Shutdown IDD < 1 ␮A

Contextual Info: a +3 V, Dual, Serial Input Complete 12-Bit DAC AD8303 FEATURES Complete Dual 12-Bit DAC Pretrimmed Internal Voltage Reference Single +3 V Operation 0.5 mV/Bit with 2.0475 V Full Scale Low Power: 9.6 mW 3-Wire Serial SPI Compatible Interface Power Shutdown IDD < 1 ␮A

KM48S8030BT-G8

Abstract: KMM366S1623BT-GL MV 42H KMM366S1623BT KMM366S1623BT-G8 KMM366S1623BT-GH KM48S8030BT-G
Contextual Info: KMM366S1623BT PC100 SDRAM MODULE Revision History Revision .0 February 1998 - Input leakage Currents (Inputs / DQ) of Component level are changed. IIL(Inputs) : ± 5uA to ± 1uA, IIL(DQ) : ± 5uA to ± 1.5uA. - Cin to be measured at VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV.

KMM366S823BT-GL

Abstract: kmm366s823bt KMM366S823BT-GH
Contextual Info: KMM366S823BT PC100 SDRAM MODULE Revision History Revision .0 February 1998 - Input leakage Currents (Inputs / DQ) of Component level are changed. IIL(Inputs) : ± 5uA to ± 1uA, IIL(DQ) : ± 5uA to ± 1.5uA. - Cin to be measured at VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV.

KMM366S824BT-G8

Abstract: KMM366S824BT-GH KMM366S824BT-GL
Contextual Info: KMM366S824BT PC100 SDRAM MODULE Revision History Revision .0 February 1998 - Input leakage Currents (Inputs / DQ) of Component level are changed. IIL(Inputs) : ± 5uA to ± 1uA, IIL(DQ) : ± 5uA to ± 1.5uA. - Cin to be measured at VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV.

KMM374S1623BT-G8

Abstract: KMM374S1623BT-GH KMM374S1623BT-GL
Contextual Info: KMM374S1623BT PC100 SDRAM MODULE Revision History Revision .0 February 1998 - Input leakage Currents (Inputs / DQ) of Component level are changed. IIL(Inputs) : ± 5uA to ± 1uA, IIL(DQ) : ± 5uA to ± 1.5uA. - Cin to be measured at VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV.

KMM374S823BT-GL

Abstract: KMM374S823BT-G8 KMM374S823BT-GH KM48S8030BT-G MV 42H
Contextual Info: KMM374S823BT PC100 SDRAM MODULE Revision History Revision .0 February 1998 - Input leakage Currents (Inputs / DQ) of Component level are changed. IIL(Inputs) : ± 5uA to ± 1uA, IIL(DQ) : ± 5uA to ± 1.5uA. - Cin to be measured at VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV.

Contextual Info: PD - 97594 IRLR6225PbF HEXFET Power MOSFET VDS 20 V RDS on max 4.0 mΩ 5.2 mΩ 48 nC (@VGS = 4.5V) RDS(on) max (@VGS = 2.5V) Qg (typical) RG (typical) 2.2 ID 42h D D S G G S D-Pak IRLR6225PbF G D S Gate Drain Source Ω A Applications • Battery Protection Switch

irlr6225

Abstract: EIA-541 HEXFET pinout
Contextual Info: PD - 97594 IRLR6225PbF HEXFET Power MOSFET VDS 20 V RDS on max 4.0 mΩ 5.2 mΩ Qg (typical) 48 nC RG (typical) 2.2 ID 42h Ω A (@VGS = 4.5V) RDS(on) max (@VGS = 2.5V) D D S G Applications G S D-Pak IRLR6225PbF G D S Gate Drain Source • Battery Protection Switch

Contextual Info: TS64MFB72V6J-T 240PIN DDR2 667 Fully Buffered DIMM 512MB With 64Mx8 CL5 Description Hot add-on and Hot Remove Capability The TS64MFB72V6J-T is a 64M x 72bits DDR2-667 Fully Transparent mode for DRAM test support Buffered DIMM. The TS64MFB72V6J-T consists of 9 pcs

ucs-1003-1

Contextual Info: UCS1003-1/2/3 USB Port Power Controller with Charger Emulation Features: • Port Power Switch with Two Current Limit Behaviors - 2.9V to 5.5V Source Voltage Range - Up to 3.0A Current 2.85A typical with 55 m On Resistance - Overcurrent Trip or Constant Current Limiting

Contextual Info: 240PIN DDR2 667 Fully Buffered DIMM 1GB With 64Mx8 CL5 TS128MFB72V6J-T Description MBIST and IBIST Test functions The TS128MFB72V6J-T is a 128M x 72bits DDR2-667 Hot add-on and Hot Remove Capability Fully Buffered DIMM. The TS128MFB72V6J-T consists of Transparent mode for DRAM test support

Contextual Info: TS128MFB72V6J-T 240PIN DDR2 667 Fully Buffered DIMM 1GB With 64Mx8 CL5 Description Hot add-on and Hot Remove Capability The TS128MFB72V6J-T is a 128M x 72bits DDR2-667 Transparent mode for DRAM test support Fully Buffered DIMM. The TS128MFB72V6J-T consists of

Contextual Info: 240PIN DDR2 667 Fully Buffered DIMM 512MB With 64Mx8 CL5 TS64MFB72V6J-T Description Hot add-on and Hot Remove Capability The TS64MFB72V6J-T is a 64M x 72bits DDR2-667 Fully Transparent mode for DRAM test support Buffered DIMM. The TS64MFB72V6J-T consists of 9 pcs

Contextual Info: 240PIN DDR2 667 Fully Buffered DIMM 2GB With 128Mx4 CL5 TS256MFB72V6K-T Description Programmable CAS Latency: 3, 4, 5 The TS256MFB72V6K-T is a 256M x 72bits DDR2-667 Automatic DDR2 DRAM bus and channel calibration Fully Buffered DIMM. The TS256MFB72V6K-T consists

1080p video DAC

Abstract: 563D EIA-861 transistor nsp 699 1080I 1080P BT601 THS8200
Contextual Info: THS8200 AllĆFormat Oversampled Component Video/PC Graphics D/A System With Three 11ĆBit DACs, CGMS Data Insertion Data Manual October 2002 DAV Digital Video/Imaging SLES032A IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications,

pm4210

Abstract: samsung S3C6410 s3c6410 ARM11 processor S3C6410 SMPS samsung SCHEMATIC DIAGRAM cartesio ARM11 processor s3c6410 I2C cartesio PM4210KD8THF pm4210c
Contextual Info: PM4210 Power management IC with battery charger and power path Final Data Features • • Integrated power path – Fully integrated DC/DC power path Vsys3.6 to 4.5V to supply the whole application directly from external sources – Two inputs up to 1.5 A each