MULTIBUS ARCHITECTURE Search Results

Multibus ii protocol

Abstract: Multibus arbitration protocol 486 system bus
Contextual Info: TO SHIBA INTEGRATED CIRCUIT BAC TECHNICAL D A T A BAC Bus Arbiter/Controller GENERAL DESCRIPTION ' The MULTIBUS II Bus Arbiter/Contro1ler (BAC) is an 84-pin, CMOS component that embodies the Arbitration and system control line functions of the MULTIBUS II

Multibus ii protocol

Abstract: Multibus arbitration protocol
Contextual Info: TOSHIBA INTEGRATED CIRCUIT BAC 8 4 1 1 0 TE C H N IC A L D A T A BAC Bus Arbiter/Controller GENERAL DESCRIPTION The MULTIBUS II Bus Arbiter/Controller (BAC) is an 84-pin, CMOS component that embodies the Arbitration and system control line functions of the MULTIBUS II

multibus cable

Abstract: WD1100 WD2797 WD1802 SA450 WD1010 WD1100-10 WD1100-13 Winchester connector 48 pin floppy disk motor head step
Contextual Info: W E S T E R N D IG ITAL C O R P O R A T I O N WD1002-MTB Multibus Winchester/Floppy Disk Controller • CONTROLS UP TO FOUR 5.25" FLOPPY DISK DRIVES • MULTIBUS INTERFACE • 16 BIT DATA BUS AND 24 BIT ADDRESSING • DMA CONTROL • PROGRAMMABLE DISK PARAMETERS

BAD02

Abstract: multibus II architecture specification
Contextual Info: - INTEGRATED CIRCUIT TOSHIBA MIC 84120 TECHNICAL DATA MIC MESSAGE INTERRUPT CONTROLLER GENERAL DESCRIPTION The Message Interrupt Controller (MIC) component implements a MULTIBUS II architecture unsolicited message passing protocol interrupt capability for iPSB bus agents.

Contextual Info: TMS320UC54025402 FIXED-POINT DIGITAL SIGNAL PROCESSOR Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus • Arithmetic Instructions With Parallel Store and Parallel Load • Conditional Store Instructions

Contextual Info: TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus • Arithmetic Instructions With Parallel Store and Parallel Load • Conditional Store Instructions 40-Bit Arithmetic Logic Unit ALU ,

S320VC

Contextual Info: TMS320VC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR I • I I V • Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus • Arithmetic Instructions With Parallel Store and Parallel Load • Conditional Store Instructions

VC5410

Contextual Info: TMS320VC5410 FIXED-POINT DIGITAL SIGNAL PROCESSOR Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus • Instructions With Two- or Three-Operand Reads • Arithmetic Instructions With Parallel Store and Parallel Load

ik 7817

Abstract: HD7 Z
Contextual Info: TMS320C54X, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS I * • Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus • Fast Return From Interrupt • On-Chip Peripherals - Software-Programmable Wait-State

TMS320VC541

Contextual Info: TMS320VC5416 FIXED-POINT DIGITAL SIGNAL PROCESSOR • Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus • 40-Bit Arithmetic Logic Unit ALU Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators

Contextual Info: TMS320UVC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus • Arithmetic Instructions With Parallel Store and Parallel Load • Conditional Store Instructions 40-Bit Arithmetic Logic Unit ALU ,

STR M 6559

Contextual Info: TMS320C54X, TMS320LC54xf TMS320VC54X FIXED-POINT DIGITAL SIGNAL PROCESSORS I * Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus • 40-Bit Arithmetic Logic Unit ALU Including a 40-Bit Barrel Shifter and Two

Contextual Info: TMS320UVC5402 FIXED-POINT DIGITAL SIGNAL PROCESSOR Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus • Arithmetic Instructions With Parallel Store and Parallel Load • Conditional Store Instructions 40-Bit Arithmetic Logic Unit ALU ,

TMS320VC541

Contextual Info: TMS320C54x, TMS320LC54X, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS • Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus • Data Bus With a Bus Holder Feature • On-Chip Peripherals - Software-Programmable Wait-State

Contextual Info: TMS320VC5420 DIGITAL SIGNAL PROCESSOR • ■ • I • I V 200-Ml PS Dual-Core DSP Consisting of Independent Subsystems A and B • Conditional Store Instructions • Output Control of CLKOUT Each Core Has an Advanced Multibus Architecture With Three Separate 16-Bit

BA021

Contextual Info: M82389 MESSAGE PASSING COPROCESSOR A MULTIBUS II BUS INTERFACE CONTROLLER Military u Highly Integrated VLSI Device • High Performance Coprocessing Functions — Offloads CPU for Communication and Bus Interfacing — 40 Megabytes/Sec Burst Transfer Speed

Contextual Info: TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 D D D D D D D D D D D D D Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit ALU ,

C5000

Abstract: TMS320C5000 TMS320VC5409 TMS320VC5409PGE 0xFF80h
Contextual Info: TMS320VC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS082B – APRIL 1999 – REVISED SEPTEMBER 1999 D D D D D D D D D D D D D Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit ALU ,

Contextual Info: TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 D D D D D D D D D D D D D Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit ALU ,

RCr20 resistors

Abstract: RCR20 C5000 SPRU131 TMS320C5000 TMS320UVC5409GGU UVC5409
Contextual Info: TMS320UVC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS102A – APRIL 1999 – REVISED AUGUST 1999 D D D D D D D D D D D D D Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit ALU ,

BA021

Abstract: MPC32389 IEEE-1296 82389 ba021p 290145 BAD22 176526
Contextual Info: in tj 82389 MESSAGE PASSING COPROCESSOR A MULTIBUS II BUS INTERFACE CONTROLLER • Highly Integrated VLSI Device — Single-Chip Interface for the Parallel System Bus IEEE 1296 — Interrupt Handling/Bus Arbitration Functions — Dual-Buffer Input and Output DMA

multibus ARCHITECTURE

Abstract: mcbsp tms 6000
Contextual Info: TMS320VC5416 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS095B – MARCH 1999 – REVISED OCTOBER 1999 D D D D D D D D D D D D D Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit ALU

Contextual Info: TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 D D D D D D D D D D D D D Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit ALU ,

BDX 28

Abstract: C5000 SPRU131 TMS320C5000 TMS320UC5409 TMS320UC5409GGU
Contextual Info: TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 D D D D D D D D D D D D D Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit ALU ,