MT90820 Search Results

sti12

Abstract: ST012 FOS100 MT90820 MT90820AL MT90820AP STO11
Contextual Info: CMOS ST-BUS FAMILY MT90820 Large Digital Switch LDX Advance Information  Features • • • • • • • • • ISSUE 1 2,048 channel non-blocking switch Maintains frame integrity on concatenated channels. Per-channel selection of minimum or constant

ECTF

Abstract: 8029A
Contextual Info: MT90823 3.3 Volt Large Digital Switch Features & Benefits Guide MT90823 Features & Benefits Guide Introduction The MT90823 is a 3.3-Volt version of the 5V MT90820 Large Digital Switch. This device is pin compatible to the MT90820, requiring only changes to the supply voltage. The inputs are 5V tolerant,

Contextual Info: MT90820 Large Digital Switch What Is It? • The MT90820 is a highly integrated large digital switch supporting up to 2048 x 2048 channels. • The MT90820 supports 16 input and 16 output streams operating at 2.048, 4.096 and 8.192 Mb/s data rates. • Two main applications apply:

Contextual Info: MITEL" CMOS ST-BUS FAMILY Large Digital Switch Preliminary Information Features • • • • • • • • • • • • MT90820 ISSUE 1 2,048 x 2,048 channel non-blocking switching at 8.192 Mb/s Per-channel variable or constant throughput delay

Contextual Info: • b S 4 c] 3 7 D OOlEhbl ÔT2 ■ CMOS ST-BUS FAMILY M ITEL MT90820 Large Digital Switch Features • 2,048 x 2,048 channel non-blocking switching at 8,192 Mb/s Per-channel variable or constant throughput delay Automatic identification of ST-BUS/GCI interfaces

MT90820

Abstract: MT90820AL MT90820AP
Contextual Info: CMOS ST-BUS FAMILY MT90820 Large Digital Switch Features DS5362 ISSUE 6 April 2000 Ordering Information • • • • • • • • • • • 2,048 x 2,048 channel non-blocking switching at 8.192 Mb/s Per-channel variable or constant throughput delay

Contextual Info: CMOS ST-BUS FAMILY MT90820 Large Digital Switch Features DS5362 ISSUE 6 April 2000 Ordering Information • • • • • • • • • • • 2,048 x 2,048 channel non-blocking switching at 8.192 Mb/s Per-channel variable or constant throughput delay

Contextual Info: MT90820A Large Digital Switch Errata Sheet Description This documents describes an erratum to Mitel Semiconductor’s Datasheet, Issue 5, April 1998 for our Large Digital Switch, MT90820A device. Problem Under certain conditions of operation and applications identified below for the MT90820A, there

D965

Contextual Info: CMOS ST-BUS FAMILY I t L MT90820 Large Digital Switch S E M IC O N D U C T O R Features ISSUE 5 2,048 x 2,048 channel non-blocking switching at 8.192 Mb/s Per-channel variable or constant throughput delay Autom atic identification of ST-BUS/GCI interfaces

MT90820

Abstract: MT90820AL MT90820AP
Contextual Info: CMOS ST-BUS FAMILY MT90820 Large Digital Switch Features DS5362 ISSUE 6 April 2000 Ordering Information • • • • • • • • • • • 2,048 x 2,048 channel non-blocking switching at 8.192 Mb/s Per-channel variable or constant throughput delay

MT90820AL

Abstract: MT90820AP1 OF100 MT90820 MT90820AL1 MT90820AP MT90820APR MT90820APR1 STO10
Contextual Info: CMOS ST-BUSTM Family MT90820 Large Digital Switch Data Sheet Features August 2005 • 2,048 x 2,048 channel non-blocking switching at 8.192 Mb/s • Per-channel variable or constant throughput delay • Automatic identification of ST-BUS/GCI interfaces •

MT90820

Abstract: MT90820AL MT90820AP
Contextual Info: CMOS ST-BUS FAMILY MT90820 Large Digital Switch Features DS5362 ISSUE 6 April 2000 Ordering Information • • • • • • • • • • • 2,048 x 2,048 channel non-blocking switching at 8.192 Mb/s Per-channel variable or constant throughput delay

siemens Logo 230 rc manual

Abstract: GR-1244-CORE MT9044 MT9044AL MT9044AP TR62411
Contextual Info: MT9044 T1/E1/OC3 System Synchronizer Data Sheet Features November 2003 • Supports AT&T TR62411 and Bellcore GR-1244CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ITU-T G.813 Option 1 clocks for 2048 kbit/s interfaces

E1210

Abstract: JT-G704 JT-G703 JT-G706 MT9072 MT9072AB MT9072AV PUB43801 PCM24 Y230
Contextual Info: MT9072 Octal T1/E1/J1 Framer Data Sheet Features • • • • • • • October 2004 Eight fully independent, T1/E1/J1 framers 3.3 V supply with 5 V tolerant inputs Selectable 2.048 Mbit/s or 8.192 Mbit/s serial buses for both data and signaling Framing Modes:

Contextual Info: MT9072 Octal T1/E1/J1 Framer Advance Information DS5063 Features • • Eight fully independent, T1/E1/J1 framers 3.3V supply with 5V tolerant inputs • Selectable 2.048 Mbit/s or 8.192 Mbit/s serial buses for both data and signaling • • Framing Modes:

Contextual Info: MT9072 Octal T1/E1/J1 Framer Advance Information Features • • • • • • • DS5063 Eight fully independent, T1/E1/J1 framers 3.3V supply with 5V tolerant inputs Selectable 2.048 Mbit/s or 8.192 Mbit/s serial buses for both data and signaling Framing Modes:

3 phase automatic change over switch circuit diagram

Contextual Info: MT9044 T1/E1/OC3 System Synchronizer DS5058 Features • • • • • • • • • • • • • Supports AT&T TR62411 and Bellcore GR-1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces Supports ITU-T G.813 Option 1 clocks for 2048

"digital switch"

Abstract: ZL50018 ZL50019 ZL50021 ZL50022 MT8986 MT89L86 MT90810 MT90863 ZL50010
Contextual Info: The Leader in TDM/TSI Switching PRODUCT CATALOG Zarlink is the global leader in TDM/TSI switching, with the industry’s largest portfolio of low-, medium-, and high-density devices with advanced features including on-board Stratum 3 timing and per-stream

MT9075

Abstract: E1 to ethernet converter circuit "network interface cards"
Contextual Info: MT90210 Multi-Channel Parallel Access Circuit Features & Benefits Guide September 14, 1998 Revision 1.0 MT90210 Features & Benefits Guide Product Summary The MT90210 is a Multi-rate Parallel Access Circuit, that allows streaming of DS0 and Nx64Kbps streams between an isochronous serial TDM bus and a

3 phase automatic change over switch circuit diagram

Abstract: GTO MODULE
Contextual Info: MT9044 T1/E1/OC3 System Synchronizer DS5058 Features • • • • • • • • • • • • • Supports AT&T TR62411 and Bellcore GR-1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces Supports ITU-T G.813 Option 1 clocks for 2048

744 043

Contextual Info: MT9072 Octal T1/E1/J1 Framer Data Sheet Features • • • • • • • March 2004 Eight fully independent, T1/E1/J1 framers 3.3 V supply with 5 V tolerant inputs Selectable 2.048 Mbit/s or 8.192 Mbit/s serial buses for both data and signaling Framing Modes:

Motorola ic

Contextual Info: MT90500 Multi-Channel ATM AAL1 SAR Features • • • • • • • • • DS5171 AAL1 Segmentation and Reassembly device compatible with Structured Data Transfer SDT as per ANSI T1.630 and ITU I.363 standards Transports 64kbps and N x 64kbps traffic over

20184

Abstract: B-2030 MT908
Contextual Info: MT90500 Multi-Channel ATM AAL1 SAR Features • • • • • • • • • DS5171 AAL1 Segmentation and Reassembly device compatible with Structured Data Transfer SDT as per ANSI T1.630 and ITU I.363 standards Transports 64kbps and N x 64kbps traffic over

T3D41

Abstract: C01100 b1566 siemens ad1 c11 isplsi1048e-70lq SN74HC04D TP338 232acse T23-A230X siemens c45
Contextual Info: 1 2 3 4 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 AMP 747846-4 P1 PD5 PD4 PD3 PD2 PD1 A A PU7 PU6 PU5 1K R18 1K R17 1K R16 1 2 0R 1K R15 R14 PU4 R13 1 2 0R 1K R12 PU3 R11 1 2 0R 1K R10 PU2 1 2 0R R9 R8 C2- C2+ C1- C1+ R1OUT R2OUT T1IN