MS00 MARKING Search Results

MS00 MARKING Result Highlights (5)

Part	ECAD Model	Manufacturer	Description	Download	Buy
2910/BQA		Rochester Electronics LLC	2910 - Microprogram Controller - Dual marked (7801701QA)	PDF
MQ80C186-12/BYA		Rochester Electronics LLC	80C186 - Microprocessor, 16-Bit -Dual marked (5962-8850102YA)	PDF
54L04/BDA		Rochester Electronics LLC	54L04 - Hex Inverter - Dual marked (M38510/02005BDA)	PDF
9936/BCA		Rochester Electronics LLC	9936 - Hex Inverter - Dual marked (M38510/03003BCA)	PDF
54AC86/SDA-R		Rochester Electronics LLC	54AC86/SDA-R - Dual marked (M38510R75202SDA)	PDF

MS00 MARKING Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
Contextual Info: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O	Original	SN74AUC00 SCES510A 000-V A114-A) A115-A)	PDF
A115-A Abstract: C101 SN74AUC00 Contextual Info: SN74AUC00 QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATE SCES510 − NOVEMBER 2003 D Optimized for 1.8-V Operation and Is 3.6-V D 1B 1Y 2A 2B 2Y 1A VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 10 3B 9 3A 6 7 8 3Y D D D D D I/O Tolerant to Support Mixed-Mode Signal Operation	Original	SN74AUC00 SCES510 000-V A114-A) A115-A) A115-A C101 SN74AUC00	PDF
Contextual Info: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O	Original	SN74AUC00 SCES510A 000-V A114-A) A115-A)	PDF
ms00 marking Contextual Info: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O	Original	SN74AUC00 SCES510A 000-V A114-A) A115-A) ms00 marking	PDF
A115-A Abstract: C101 SN74AUC00 Contextual Info: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O	Original	SN74AUC00 SCES510A 000-V A114-A) A115-A) A115-A C101 SN74AUC00	PDF
A115-A Abstract: C101 SN74AUC00 Contextual Info: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O	Original	SN74AUC00 SCES510A 000-V A114-A) A115-A) A115-A C101 SN74AUC00	PDF
A115-A Abstract: C101 SN74AUC00 Contextual Info: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O	Original	SN74AUC00 SCES510A 000-V A114-A) A115-A) A115-A C101 SN74AUC00	PDF
Contextual Info: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O	Original	SN74AUC00 SCES510A 000-V A114-A) A115-A)	PDF
Contextual Info: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O	Original	SN74AUC00 SCES510A 000-V A114-A) A115-A)	PDF
A115-A Abstract: C101 SN74AUC00 Contextual Info: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O	Original	SN74AUC00 SCES510A 000-V A114-A) A115-A) A115-A C101 SN74AUC00	PDF
Contextual Info: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O	Original	SN74AUC00 SCES510A 000-V A114-A) A115-A)	PDF
Contextual Info: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O	Original	SN74AUC00 SCES510A 000-V A114-A) A115-A)	PDF
A115-A Abstract: C101 SN74AUC00 Contextual Info: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O	Original	SN74AUC00 SCES510A 000-V A114-A) A115-A) A115-A C101 SN74AUC00	PDF
Contextual Info: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 10 3B 9 3A 6 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O	Original	SN74AUC00 SCES510A 000-V A114-A) A115-A)	PDF