MODELSIM 5.4E Search Results

MODELSIM 5.4E Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
APEX20KE Abstract: ModelSim 5.4e Contextual Info: Using ModelSim-Altera in a Quartus II Design Flow December 2002, ver. 1.2 Introduction Application Note 204 This application note is a getting-started guide to using ModelSimR-Altera software in AlteraR programmable logic device PLD design flows. Proper functional and timing simulation is important to ensure design	Original	apex20ke modelsim 5.4e	PDF
block diagram code hamming using vhdl Abstract: hamming test bench vhdl code hamming window vhdl code hamming vhdl code for 8 bit parity generator hamming code FPGA block diagram code hamming hamming code in vhdl vhdl code for 4 bit even parity generator TPC encoder design using xilinx Contextual Info: IEEE 802.16-Compatible Turbo Product Code Encoder v1.0 DS211 June 30, 2008 Product Specification Features LogiCORE Facts • Performs TPC encoding as defined in the IEEE 802.16 and 802.16a standards • Optimized for Virtex -II and Virtex-II Pro FPGAs,	Original	16-compatible ds211 block diagram code hamming using vhdl hamming test bench +8vhdl code hamming window vhdl code hamming vhdl code for 8 bit parity generator hamming code fpga block diagram code hamming hamming code in vhdl vhdl code for 4 bit even parity generator tpc encoder design using xilinx	PDF
SPARTAN XCS40XL Abstract: XCS40XL Sierra-16 XC2V1000 XC2V2000-5 Contextual Info: Sierra-16 Operating System Accelerator July 26, 2002 Product Specification AllianceCORE Facts RealFast Skivfilargränd 2 S – 721 30 Västerås SWEDEN Phone: +46 0 21 – 470 20 25 Fax: +46 (0)21 – 470 21 25 Email: info@realfast.se URL: http://www.realfast.se/	Original	sierra-16 spartan xcs40xl xcs40xl xc2v1000 +1xc2v2000-5	PDF
ACTEL proASIC PLUS Abstract: A500K050-PQ208 ModelSim 5.4e DCOM98 verilog code for timer Contextual Info: Designer Series Development System R1-2001 Release Notes This document describes the new features and enhancements of the Designer Series Development System R1-2001 release. It also contains information about discontinued features and known limitations. For the latest information about which versions of Cadence, Mentor	Original	r1-2001 dcom98 r1-2001r actel proasic plus +3a500k050-pq208 modelsim 5.4e verilog code for timer	PDF
CRC16 Abstract: CRC-16 XILINX EEprom ModelSim 5.4e crc 16 verilog Contextual Info: MC-XIL-USB11DEV USB 1.1 Device Controller May 20, 2002 Product Specification AllianceCORE Facts Powered by 0HPHF&RUHTM Product Line 9980 Huennekens Street San Diego, CA 92121 Americas:+1 888-360-9044 Europe: +1 41 0 32 374 32 00 Asia: +(852) 2410 2720	Original	mc-xil-usb11dev crc16 crc-16 xilinx eeprom +2modelsim 5.4e crc 16 verilog	PDF
BPSK modulation VHDL CODE Abstract: vhdl code for bpsk modulation 16 bit qpsk VHDL CODE hardware implementation of bpsk bpsk simulink matlab QPSK using xilinx qpsk simulink matlab system generator matlab ise qpsk modulation VHDL CODE Signal-to-noise ratio matlab Contextual Info: Additive White Gaussian Noise AWGN Core v1.0 DS210 October 30, 2002 Product Specification Features LogiCORE Facts • Designed for Virtex™-II and Virtex-II Pro™ using structural VHDL • Probability density function (PDF) deviates less than 0.2 percent from the Gaussian PDF for \|x\| < 4.8σ and is	Original	ds210 bpsk modulation vhdl code vhdl code for bpsk modulation 16 bit qpsk vhdl code +7hardware implementation of bpsk bpsk simulink matlab qpsk using xilinx qpsk simulink matlab system generator matlab ise qpsk modulation vhdl code signal-to-noise ratio matlab	PDF
CS5230 Abstract: cs6100 CS5220 CS-524 cs5240 CS5210-40 XCV100E power AES 256 encryption 32 bit CS5200 CS52-10 Contextual Info: High-Performance Encryption Cores January 28, 2002 Product Specification AllianceCORE Facts Core Specifics See Table 1 Provided with Core TM Amphion Semiconductor, Ltd. 50 Malone Road Belfast BT9 5BS Northern Ireland Phone: +44 28 9050 4000 Fax: +44 28 9050 4001	Original	128-bit 256-bit 32-bit cs5230 +9cs6100 cs5220 cs-524 cs5240 cs5210-40 xcv100e power aes 256 encryption 32 bit cs5200 cs52-10	PDF
CS5200 Abstract: CS5250-80 556 pinout diagram data encryption standard vhdl CS-527 wireless ciphertext Contextual Info: High-Performance Decryption Cores January 28, 2002 Product Specification AllianceCORE Facts Core Specifics See Table 1 Provided with Core TM Amphion Semiconductor, Ltd. 50 Malone Rd Belfast BT9 5BS Northern Ireland Phone: +44 28 9050 4000 Fax: +44 28 9050 4001	Original	128-bit 256-bit 32-bit cs5200 +5cs5250-80 556 pinout diagram data encryption standard vhdl cs-527 wireless ciphertext	PDF
turbo encoder circuit, VHDL code Abstract: turbo codes matlab simulation program turbo codes matlab code 5 to 32 decoder using 38 decoder vhdl code hamming decoder vhdl code 4 bit SISO vhdl code hamming block diagram code hamming Comtech Aha 4501 vhdl coding for hamming code Contextual Info: IEEE 802.16-Compatible Turbo Product Code Decoder v1.1 DS212 June 30, 2008 Product Specification Features • Performs decoding for the turbo product codes listed in the IEEE 802.16 and 802.16a standards • Optimized for Virtex -II and Virtex-II Pro FPGAs	Original	16-compatible ds212 turbo encoder circuit, vhdl code turbo codes matlab simulation program +8turbo codes matlab code 5 to 32 decoder using 38 decoder vhdl code hamming decoder vhdl code 4 bit siso vhdl code hamming block diagram code hamming comtech aha 4501 vhdl coding for hamming code	PDF
vhdl code 64 bit FPU Abstract: vhdl code for march c algorithm vhdl code for pipelined matrix multiplication ieee floating point vhdl vhdl code for FFT 32 point ML403 UART ml403 vhdl code for matrix multiplication vhdl code for floating point matrix multiplication XILINX UART lite Contextual Info: APU Floating-Point Unit v3.1 March 11, 2008 Product Specification Introduction LogiCORE Facts The Xilinx Auxiliary Processor Unit APU Floating-Point Unit LogiCORETM is a single-precision floating-point unit designed for the PowerPCTM 405 embedded microprocessor of the VirtexTM-4 FX FPGA	Original	vhdl code 64 bit fpu vhdl code for march c algorithm vhdl code for pipelined matrix multiplication ieee floating point vhdl +6vhdl code for fft 32 point ml403 uart ml403 vhdl code for matrix multiplication vhdl code for floating point matrix multiplication xilinx uart lite	PDF
7809 data sheet national semiconductor Abstract: design of FM reciever final year project vhdl code for traffic light control cofdm modem chip coder vhdl code for ofdm APEX 20ke development board sram OTU2 framer vhdl code for ofdm transmitter vhdl cyclic prefix code download vhdl code for FM RECIEVER Contextual Info: & News Views First Quarter 2001 The Programmable Solutions Company® Newsletter for Altera Customers Altera Unleashes Quartus II Software Version 1.0 Altera’s new QuartusTM II software delivers dramatic improvements in design performance fMAX , compilation times, and designer	Original	240-pin epm9560a 208-pin 356-pin +13epm9560 280-pin 304-pin 7809 data sheet national semiconductor design of fm reciever final year project vhdl code for traffic light control cofdm modem chip coder vhdl code for ofdm apex 20ke development board sram otu2 framer vhdl code for ofdm transmitter vhdl cyclic prefix code download vhdl code for fm reciever	PDF
7809 voltage regulator datasheet Abstract: 7809 voltage regulator voltage regulator 7809 INL03991-02 7809 data sheet national semiconductor embedded system projects pdf free download toshiba web cam TB62705 ST 7809 voltage regulator excalibur Board Contextual Info: & News Views Second Quarter 2001 Newsletter for Altera Customers Altera Provides the Complete I/O Solution with the New APEX II Device Family Altera introduces the APEXTM II device family— flexible, high-performance, high-density programmable logic devices PLDs that deliver	Original	624-megabit 7809 voltage regulator datasheet 7809 voltage regulator voltage regulator 7809 +7inl03991-02 7809 data sheet national semiconductor embedded system projects pdf free download toshiba web cam tb62705 st 7809 voltage regulator excalibur board	PDF