MODE OPERATION Search Results

Regulator AE

Abstract: RP200x
Contextual Info: RP200x Series Automatic Mode Shift 300mA LDO The RP200x Series are CMOS-based automatic mode shift LDO regulators featuring 300mA output. In auto switching mode, the operation can switch automatically to fast response mode or low power mode of the ECO function

Contextual Info: RP200x Series Manual/Automatic Mode Shift Low Voltage 300mA LDO The RP200x Series are CMOS-based manual/automatic mode shift LDO regulators featuring 300mA output. In auto switching mode, the operation can switch automatically to fast response mode or low power mode of the ECO function according to output current.

Contextual Info: RP201x Series Manual/Automatic Mode Shift Low Voltage 150mA LDO The RP201x Series are CMOS-based manual/automatic mode shift LDO regulators featuring 150mA output. In auto switching mode, the operation can switch automatically to fast response mode or low power mode of the ECO function according to output current.

Z80180

Abstract: Z8018008PSC Z8L180 Z8S180 Z8S180 instruction manual
Contextual Info: Z8018x Family MPU User Manual 281 Operating Modes Summary REQUEST ACCEPTANCES IN EACH OPERATING MODE Table 53. Current Normal Status Operation CPU mode and IOSTOP Request Mode Request Acceptances in Each Operating Mode Refresh WAIT State Cycle Interrupt

Contextual Info: R5326x Series Automatic Mode Shift Low Voltage Dual 150mA LDO The R5326x Series are CMOS-based auto mode switching dual LDO regulators featuring 150mA output. In auto switching mode, the operation can switch automatically to a fast response mode or a low power mode of the ECO function according to output current.

VIC068A

Abstract: CY7C960 CY7C964 MD32
Contextual Info: 3.9 I/O Control Description The CY7C960 has two basic modes of operation: DRAM mode and I/O mode. The user selects the mode during configuration. This section describes the I/O mode of operation. In I/O mode the CY7C960 does not provide the timing signals required by DRAM, such as

HT56R6x

Contextual Info: HT56R6x MCU Operating Mode Introduction HT56R6x MCU Operating Mode Introduction D/N：HA0179E Introduction The HT56R6x series of MCUs provide a range of different clocks for the different internal functional modules and provides multiple mode operation with dynamic mode switching.

AND8123

Abstract: MC33262 IEC1000 MC33260 MC33368 NCP1650 flyback pfc using constant on-time MC33260 equivalent 32P2T CCM PFC inductor analysis
Contextual Info: AND8123/D Power Factor Correction Stages Operating in Critical Conduction Mode Prepared by: Joel Turchi ON Semiconductor http://onsemi.com APPLICATION NOTE Basics of the Critical Conduction Mode Critical conduction mode or border line conduction mode operation is the most popular solution for low power

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT U P D 42S 18165, 4218165 16 M-BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, HYPER PAGE MODE, BYTE READ/WRITE MODE description The,uPD42S18165,4218165 are 1,048,576 words by 16 bits CMOS dynamic RAMs with optional hyper page mode. Hyper page mode is a kind of the page mode and is useful for the read operation.

ICR03

Abstract: 170H 171H 2.1 Introduction memory card addressing mode
Contextual Info: REFERENCE MANUAL 2 CHAPTER 2 Z86017/Z16017 ADDRESSING MODES 2.1 INTRODUCTION The 017 supports all PCMCIA Addressing Modes: • PCMCIA Common Memory Mode ■ PCMCIA I/O Mode ■ PCMCIA ATA_IDE Mode ■ Pass-through ATA/IDE-to-ATA/IDE Mode* The overall 017 mode of operation is controlled by the Interface Configuration Register 00H bits 3,2. A 00 in these

M1061

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD421165 1 M-BIT DYNAMIC RAM 64K-WORD BY 16-BIT, HYPER PAGE MODE EDO , BYTE READ/WRITE MODE Description The µPD421165 is a 65,536 words by 16 bits CMOS dynamic RAM with optional hyper page mode (EDO). Hyper page mode (EDO) is a kind of the page mode and is useful for the read operation.

D-31M

Contextual Info: D-31M OPERATION MANUAL Driver for MID-IR LEDs, QCW and Pulse Mode 1. Application The driver D-31M is designed as power supply of Mid-IR LEDs. 2. Features • The driver D-31M provides two modes of operation: Quasi Continuous Wave mode the mode of maximum average optical power from the LED and pulse mode (the mode of maximum

HY514100A

Abstract: HY514100ALT HY514100AJ 4Mx1
Contextual Info: HY514100A 4Mx1, Fast Page mode DESCRIPTION This family is a 4M bit dynamic RAM organized 4,194,304 x 1-bit configuration with Fast Page mode CMOS DRAMs. Extended data out mode is a kind of page mode which is useful for the read operation. The circuit and process

ic 8279 block diagram

Abstract: 8279 intel microprocessor pin diagram ic 8279 Block Diagram of 8279 applications of 8279 8279 8279-5 ic 8279 intel 8279 decoder m8279a
Contextual Info: in te i 8 2 7 9 /8 2 7 9 -5 PROGRAMMABLE KEYBOARD/DISPLAY INTERFACE Simultaneous Keyboard Display Operations Single 16-Character Display Scanned Keyboard Mode Right or Left Entry 16-Byte Display RAM Scanned Sensor Mode Mode Programmable from CPU Strobed Input Entry Mode

1Mx4 EDO RAM

Abstract: 1Mx4 EDO DRAM HY514404A schematic diagram UPS
Contextual Info: HY514404A 1Mx4, Extended Data Out mode DESCRIPTION This family is a 4M bit dynamic RAM organized 1,048,576 x 4-bit configuration with Extended Data Out mode CMOS DRAMs. Extended data out mode is a kind of page mode which is useful for the read operation. The circuit and process

1Mx4 EDO RAM

Abstract: 1Mx4 HY514404B
Contextual Info: HY514404B 1Mx4, Extended Data Out mode DESCRIPTION This family is a 4M bit dynamic RAM organized 1,048,576 x 4-bit configuration with Extended Data Out mode CMOS DRAMs. Extended data out mode is a kind of page mode which is useful for the read operation. The circuit and process

M513

Abstract: MADCSM0001 MADCSM0001SMB MADCSM0001TR
Contextual Info: Dual-Band/Triple-Mode Downconverter 869 - 893 MHz and 1930 - 1990 MHz Functional Block Diagram Features MODE SEL MODE SEL VDD CELL SRC CELL VDD Highly Integrated Downconverter Operates over 2.8 V to 5 V Supply Voltage Dual-Band and Triple-Mode Operation High Linearity, IP3 = 10 dBm typical

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT ¿¿PD 4211 7 5 1 M-BIT DYNAMIC RAM 64K-WORD BY 16-BIT, HYPER PAGE MODE EDO , BYTE WRITE MODE Description The /¿PD421175 is a 65,536 words by 16 bits CMOS dynamic RAM with optional hyper page mode (EDO). Hyper page mode (EDO) is a kind of the page mode and is useful for the read operation.

Contextual Info: N EC MOS INTEGRATED CIRCUIT ju P D 4216165 16 M-BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, HYPER PAGE MODE, BYTE READ/WRITE MODE Description The ¿IPD4216165 is a 1 048 576 words by 16 bits dynamic C M O S RAM with optional hyper page mode. Hyper page mode is a kind of the page mode and is useful for the read operation,

kdrc

Contextual Info: CURRENT-MODE MODELING FOR PEAK, VALLEY AND EMULATED CONTROL METHODS Reference Guide for Fixed-Frequency, Continuous Conduction-Mode Operation Robert Sheehan Principal Applications Engineer National Semiconductor Corporation Santa Clara, CA Current-Mode Control

hy5117804c

Contextual Info: HY5117804C,HY5116804C 2Mx8, Extended Data Out mode DESCRIPTION This family is a 16M bit dynamic RAM organized 2,097,152 x 8-bit configuration with Extended Data Out mode CMOS DRAMs. Extended data out mode is a kind of page mode which is useful for the read operation. The circuit and process

hy5117404c

Contextual Info: HY5117404C,HY5116404C 4Mx4, Extended Data Out mode DESCRIPTION This family is a 16M bit dynamic RAM organized 4,194,304 x 4-bit configuration with Extended Data Out mode CMOS DRAMs. Extended data out mode is a kind of page mode which is useful for the read operation. The circuit and process

HY51V17404C

Contextual Info: HY51V17404C,HY51V16404C 4Mx4, Extended Data Out mode DESCRIPTION This family is a 16M bit dynamic RAM organized 4,194,304 x 4-bit configuration with Extended Data Out mode CMOS DRAMs. Extended data out mode is a kind of page mode which is useful for the read operation. The circuit and process

HY5117400B

Abstract: HY5116400B HY5117400 4Mx4 DRAM
Contextual Info: HY5117400B,HY5116400B 4Mx4, Fast Page mode DESCRIPTION This family is a 16M bit dynamic RAM organized 4,194,304 x 4-bit configuration with Fast Page mode CMOS DRAMs. Fast Page mode is a kind of page mode which is useful for the read operation. The circuit and process design allow this