MDIO PHY Search Results

1000BASE-T2

Abstract: MDIO clause 22 clause 22 phy registers wishbone RD1074 MDIO MDIO controller 3 to 8 bit decoder vhdl IEEE format LCMXO640C-4T100C 100Base-T2
Contextual Info: Accessing Control Registers Through the MDIO Bus February 2010 Reference Design RD1074 Introduction Management Data Input/Output Interfaces, or MDIO, are specified in the IEEE 802.3 standard. Their primary application is to provide a Serial Management Interface SMI to transfer management data between an Ethernet Media

TX2C

Abstract: RD2 TP10 GT48300 gt-48300 GT-48310 TX3C 6r190 GT48310A CDATA14 gt48310
Contextual Info: A B C configuration rxd0[1:0] txd0[1:0] rxd7[1:0] txd7[1:0] e_cs e_clk e_di e_do endev* limit4 Test Points 4 rxd0[1:0] txd0[1:0] main_clk rst* txen[7:0] txen[7:0] 4 d_cs* d_we* d_ras* d_cas* d_DQM mdio mdc mdio mdc CRS_dv[7:0] d_data[31:0] d_addr[11:0] d_data[31:0]

QT2042

Abstract: qt2044 10GBASE-CX4 XGXS
Contextual Info: PRODUC T BRIEF 042 QT2 M QT2042/QT2044 3.125 Gb/s XAUI Physical Layer IC for 10GBASE-LX4 and 10GBASE-CX4 Applications Features Description • 10GE, 10GFC data rate support • Compliant to IEEE802.3ae standard, and XENPAK MSA • MDC/MDIO and EEPROM interface

SPRU401

Abstract: MDIO tms320c64x teardown C6000 SPRU189 SPRU190 TMS320C6000 SPRU628A
Contextual Info: TMS320C6000 DSP Ethernet Media Access Controller EMAC / Management Data Input/Output (MDIO) Module Reference Guide Literature Number: SPRU628A March 2004 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

BCM8706

Abstract: 10G BIST PRBS 64b/66b encoder gearbox microcontroller optics fiber MDIO clause 45 XAUI 8706p 10G serdes 2.5 xaui
Contextual Info: BCM8706 XAUI TO SERIAL 10G BASE-LRM TRANSCEIVER SUMMARY OF BENEFITS FEATURES • Meets and exceeds industry standard • IEEE 802.3ae • IEEE802.3aq • MDIO interface compliant to IEEE 802.3ae Clause 45 with extended indirect address register access

jabber

Abstract: 23Z128 TNETE2004 TNETX15VEPGE TNETX3150
Contextual Info: TNETE2004 MDIO-MANAGED QuadPHY FOUR 10BASE-T PHYSICAL-LAYER INTERFACES SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997 D D D D D D D D Single-Chip Multi-PHY Solution: – Four 10BASE-T Physical-Layer PHY Interfaces in One Package Minimizing PCB Footprint for Internetworking

Contextual Info: TNETE2004 MDIO-MANAGED QuadPHY FOUR 10BASE-T PHYSICAL-LAYER INTERFACES SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997 D D D D D D D D Single-Chip Multi-PHY Solution: – Four 10BASE-T Physical-Layer PHY Interfaces in One Package Minimizing PCB Footprint for Internetworking

Contextual Info: TNETE2004 MDIO-MANAGED QuadPHY FOUR 10BASE-T PHYSICAL-LAYER INTERFACES SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997 D D D D D D D D Single-Chip Multi-PHY Solution: – Four 10BASE-T Physical-Layer PHY Interfaces in One Package Minimizing PCB Footprint for Internetworking

Marvell fibre copper

Abstract: marvell alaska marvell IEEE
Contextual Info: Transceiver Solutions Alaska X 10GBASE-CX4 Transceiver 88X2088 PRODUCT OVERVIEW Dev. 4 PHY XGXS L0 L1 L2 L3 L0 L1 L2 L3 LASI Deserializer 8B/10B Decoder FIFO Dev. 3 PCS 8B/10B Encoder Serializer 8B/10B Encoder FIFO 8B/10B Decoder LASI MDC MDIO INTn Management

PBD14

Abstract: PBD26 PBD24 PBD12 ALLAYER COMMUNICATIONS PBD30 ETD12 PBD18 PBD-28 ETD10
Contextual Info: AL15 Revision 1.0 5-PORT LOW COST 10/100 SWITCH WITH RMII • • • • • • • • Supports five 10/100 Mbit/s Ethernet ports with RMII interface Capable of trunking up to 500 Mbit/s link Full- and half-duplex mode operation Speed auto-negotiation through MDIO

88X2012

Abstract: MARVELL "XAUI to XFI" 10 Gbps phy XFP-10 802.3ae MDIO x-10 transmitter xaui marvell XFP EVALUATION BOARD optical encoder module media converter optical fibre
Contextual Info: Transceiver Solutions Alaska X 10 Gigabit Serial to XGMII Transceiver 88X2012 PRODUCT OVERVIEW TXD[31:0] TXC[3:0] TX_CLK FIFO 64B/66B Encoder Serializer RXD[31:0] RXC[3:0] RX_CLK FIFO 64B/66B Decoder Deserializer TBG/Clock Synthesizer MDC MDIO INTn Management

MDIO clause 45

Contextual Info: PC-I2C-KIT with MDIO and SPI support Quick Start Manual FDI Future Designs, Inc. Your Development Partner Information in this document is provided solely to enable the use of Future Designs, Inc. products. FDI assumes no liability whatsoever, including infringement of any patent or copyright. FDI

AL15

Abstract: SGRAM
Contextual Info: AL15 Advance Information Five-Port Low Cost 10/100 Switch With RMII • • • • • • • • Supports five 10/100 Mbit/s Ethernet ports with RMII interface Capable of trunking up to 500 Mbit/s link Full- and half-duplex mode operation Speed auto-negotiation through MDIO

LF9203

Abstract: Pulse bob smith termination TG1G-S002NZ VFAC570BL Delta LF9203 H5008 H5007 driver TG1G VCC1-B2B-125M000 C04305L
Contextual Info: National Semiconductor Application Note 1263 Leo Chang Patrick O'Farrell September 8, 2010 1.0 Introduction The active low RESET should be held low for a minimum of 150 µs to allow power supply voltage and clock input to stablize before starting internal initialization. The first MDIO access should wait another 500 µs till internal initialization is

MDIO

Abstract: MDIO clause 45 MDIO clause 45 specification vhdl code for mac interface 10GBASE-X datasheets of optical fpgas giga media converter 10GBASE-LX4 UCF virtex-4 ffs 642
Contextual Info: XAUI v8.2 DS266 June 24, 2009 Product Specification Introduction LogiCORE IP Facts The LogiCORE IP XAUI core is a high-performance, low pin count 10-Gbps interface intended to allow physical separation between data-link layer and physical layer devices in a 10-Gigabit Ethernet system.

2C213

Abstract: C023H QT2022 190B PHILIPS QT2032 QT2032PRKCB LBGA thermal QT2032PBKCB CC08h CC01h
Contextual Info: QT2022/32 - Data Sheet: DS3051 10 Gb/s Serial-to-XAUI PHY ICs for Ethernet and Fibre Channel LAN/ SAN/WAN Applications CDR April 7, 2010 1 Description The QT2032 and QT2022 products are fully integrated PHY ICs designed for use in 10 Gb/s IEEE 802.3-2005

100Base-T2

Abstract: MDIO 100BASET2 MDIO MDC 1000BASE-X CYP32G0401DX
Contextual Info: Management Interface Application Note for the CYP32G0401DX History period for MDC is 400ns. Levels will be defined later in this note. The management interface as defined in IEEE802.3 is a simple two wire serial interface, which connects a STA Station Management Entity and a managed PHY (Physical Layer

MDIO clause 45 specification

Abstract: Virtex-7 serdes xilinx tcp vhdl MDIO 10G Ethernet MAC virtex 5 ddr data path virtex7 xilinx kintex virtex-7 kintex 7
Contextual Info: LogiCORE IP 10-Gigabit Ethernet PCS/PMA v2.1 DS739 March 1, 2011 Product Specification Introduction The LogiCORE IP 10-Gigabit Ethernet PCS/PMA core forms a seamless interface between the Xilinx 10-Gigabit Ethernet Media Access Controller MAC and a 10 Gb/s-capable PHY, enabling the design of

sm 41056

Abstract: 5535 12 r4 opto 10GBASE-LR HFCT-701XBD RIN12OMA 10GBASE-LW 10 gb laser diode 10G serdes
Contextual Info: Agilent HFCT-701XBD, 10 Gb Ethernet, 1310 nm, 10 km 10GBASE-LR, XENPAK LAN-PHY Data Sheet Description The HFCT-701XBD is an “intelligent” optical module which incorporates the complete physical layer functionality from the 10.3125 Gb/s 64B/66B encoded optical

49153

Abstract: 8049 encoder HFCT-701XB 10GBASE-LR HFCT701XB RIN12OMA
Contextual Info: Agilent HFCT-701XB, 10 Gb Ethernet, 1310 nm, 10 km 10GBASE-LR, XENPAK LAN-PHY Data Sheet Description The HFCT-701XB is an “intelligent” optical module which incorporates the complete physical layer functionality from the 10.3125 Gb/s 64B/66B encoded optical interface to a

807b

Abstract: hfct701xb
Contextual Info: Agilent HFCT-701XB, 10 Gb Ethernet, 1310 nm, 10 km 10GBASE-LR, XENPAK LAN-PHY Data Sheet Description The HFCT-701XB is an “intelligent” optical module which incorporates the complete physical layer functionality from the 10.3125 Gb/s 64B/66B encoded optical interface to a

DP83640

Abstract: high speed parallel to usb IC connector AFBR-5803Z R117 R118 R128 R139 parallel to usb IC connector DP83640 software EVK 233
Contextual Info: 10/100 Mb/s Ethernet Products DP83640 Precision PHYTER IEEE 1588 Precision Time Protocol Transceiver Demo Board User Guide Interface Division April 16, 2008 Document Revision B Table of Contents 1 2 General Description. 1

TLK3114SA

Contextual Info: DLKPC192S 10ĆGbps ETHERNET LAN PHYSICAL CODING SUBLAYER PCS WITH SSTL XGMII INTERFACE SLLS536 – AUGUST 2002 D 10-Gbps Ethernet LAN PCS With 64b/66b D D ENDEC 10-Gbps Media-Independent Interface (XGMII) Using 2.5-V SSTL Class 2 Technology 10-Gbps 16-Bit Interface (XSBI) Using LVDS

LXT970AHC

Abstract: digital clock circuit 14053b HALO TG110 rj45 LXT970AQC 100BASE-FX LXT970 LXT970A E1 to fiber optic converter circuit HALO TG110-S050N2
Contextual Info: DATA SHEET JULY 1998 Revision 1.0 LXT970A Dual-Speed Fast Ethernet Transceiver General Description Features The LXT970A is an enhanced derivative of the LXT970 10/100 Mbps Fast Ethernet PHY Transceiver with selectable driver strength capabilities and link-loss criteria.