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    MATLAB SOURCE Search Results

    MATLAB SOURCE Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    UDS2981R/B
    Rochester Electronics LLC UDS2981 - High Voltage, High Current Source Driver PDF Buy
    UDS2983R/B
    Rochester Electronics LLC UDS2983 - High Voltage, High Current Source Driver PDF Buy
    LM334Z/LFT1
    Texas Instruments 3-Terminal Adjustable Current Source 3-TO-92 Visit Texas Instruments Buy
    LM134H/NOPB
    Texas Instruments 3-Terminal Adjustable Current Source 3-TO -55 to 125 Visit Texas Instruments Buy
    TPS51200TDB1
    Texas Instruments Sink/Source DDR Termination Regulator 0- Visit Texas Instruments

    MATLAB SOURCE Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    cxa FM radio

    Abstract: matlab N9030A MXA agilent N6171A 5989-9377EN N9010A N9010 AGILENT 9030A 5989-4942EN
    Contextual Info: Agilent N6171A MATLAB Data Analysis Software for X-Series and PSA Series Signal and Spectrum Analyzers Technical Overview • Enhance your Agilent signal and spectrum analyzers with the data analysis power of MATLAB software Create and execute your own analysis routines and


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    n6171a5989-9723encxa fm radiomatlab+7n9030amxa agilent5989-9377enn9010an9010agilent 9030a5989-4942en PDF

    matlab

    Abstract: DSO80000A Butterworth N5430A 5989-7819EN DSO80000B DSO90000 E2688A E2699A N5400A
    Contextual Info: Agilent N5430A Infiniium User-Defined Function Application for Infiniium Oscilloscopes Data Sheet • Enhance your Infiniium oscilloscope with the analysis power of MATLAB software • Develop custom analysis functions directly on Infiniium oscilloscopes


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    n5430a5989-5632enmatlabdso80000a+7butterworth5989-7819endso80000bdso90000e2688ae2699an5400a PDF

    Contextual Info: Agilent N8806A User Defined Function for Editing and Execution for Infiniium Oscilloscopes Data Sheet • Create your own custom functions or modify included functions using the power of MATLAB software • Enables Infiniium oscilloscopes to execute customized math and


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    n8806awishe295990-9174en PDF

    fir filter design using vhdl

    Abstract: farrow FIR filter matlaB simulink design AN-347-1 VHDL for decimation filter FIR filter matlaB design Resampler sample rate converter AN3471
    Contextual Info: Farrow-Based Decimating Sample Rate Converter Application Note AN-347-1.0 Introduction The Farrow-based decimating sample rate converter demonstrates a Farrow resampler. The converter is supplied with the Altera DSP Builder version 2.2.0. You can simulate its performance in MATLAB, change it as


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    an-347-1fir filter design using vhdlfarrowfir filter matlab simulink design+5vhdl for decimation filterfir filter matlab designresamplersample rate converteran3471 PDF

    Contextual Info: TravelScope DSO • PC-based, USB2.0 interface / powered • 2 channels stackable to 12 channels • 1 GS/s sampling, 200 MHz bandwidth • Export data to WORD, EXCEL, TEXT, HTML, MATLAB etc. • Trigger Group I : Edge, External, Width, Video / TV • Trigger Group II : A-B, Delay, Pattern, Runt, Setup / Hold, State, Timeout,


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    ts2202ets2212ets2212ats2212h+1ts2202e/ts2212e/ts2212a PDF

    st pl001

    Abstract: AN3138 matlab STEVAL-MKI062V1 MEMS pressure sensor MATLAB inemo pl001 accelerometer magnetometer pressure sensor MATLAB STM32F103Rx
    Contextual Info: AN3138 Application note Wrapper in MATLAB for the STEVAL-MKI062V1 Introduction This application note provides information on the use of the application programming interface API of the iNEMO software development kit (SDK), which provides easy-to-use function calls to obtain data from the sensors or to change settings. The dynamic link library


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    an3138steval-mki062v1st pl001matlab+6mems pressure sensor matlabinemopl001accelerometer magnetometerpressure sensor matlabstm32f103rx PDF

    FPGA XC6VSX315T-FF1156

    Abstract: fir compiler xilinx ff1136 ff1156 xc6vsx315t-ff1156 xc5vsx50t FIR filter matlaB simulink design simulink based program design for implementation FIR Filter matlab system generator matlab ise
    Contextual Info: Application Note: All Virtex and Spartan FPGA Families Source Control and Team-Based Design in System Generator XAPP498 v1.0 January 15, 2010 Summary Author: Douang Phanthavong This application note provides an overview on how to perform source version control and


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    xapp498fpga xc6vsx315t-ff1156fir compiler xilinxff1136+7ff1156xc6vsx315t-ff1156xc5vsx50tfir filter matlab simulink designsimulink based program design for implementationfir filter matlabsystem generator matlab ise PDF

    64 point FFT radix-4 VHDL documentation

    Abstract: matlab code for half adder FSK matlab CORDIC to generate sine wave fpga simulink 3 phase inverter vhdl code for ofdm verilog code for fir filter using DA fft algorithm verilog 16-point radix-4 advantages vhdl code for radix-4 fft lfsr galois
    Contextual Info: DSP Guide for FPGAs Lattice Semiconductor Corporation 5555 NE Moore Court Hillsboro, OR 97124 503 268-8000 September 2009 Copyright Copyright 2009 Lattice Semiconductor Corporation. This document may not, in whole or part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machinereadable form without prior written consent from Lattice Semiconductor


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    64 point fft radix-4 vhdl documentationmatlab code for half adderfsk matlabcordic to generate sine wave fpga+6simulink 3 phase invertervhdl code for ofdmverilog code for fir filter using dafft algorithm verilog 16-point radix-4 advantagesvhdl code for radix-4 fftlfsr galois PDF

    EP2C35

    Abstract: EP2S180 Blockset
    Contextual Info: DSP Builder Release Notes Release Notes June 2007, Version 7.1 SP1 These release notes for the DSP Builder software, v7.1 SP1 contain the following information: • ■ ■ ■ ■ ■ ■ ■ System Requirements System Requirements New Features & Enhancements


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    r2006ar2006br2007a32-bit+3ep2c35ep2s180blockset PDF

    DSP processor latest version in 2010

    Abstract: r2008b vhdl code for FFT 32 point jpeg encoder vhdl code matlab multimedia projects based on matlab fpga based Numerically Controlled Oscillator dsp processor design using vhdl filter design software design filter matlaB software design
    Contextual Info: DSP Builder Handbook Volume 1: Introduction to DSP Builder 101 Innovation Drive San Jose, CA 95134 www.altera.com HB_DSPB_INTRO-1.0 Document Version: Document Date: 1.0 July 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other


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    dsp processor latest version in 2010r2008bvhdl code for fft 32 pointjpeg encoder vhdl code+6matlabmultimedia projects based on matlabfpga based numerically controlled oscillatordsp processor design using vhdlfilter design software designfilter matlab software design PDF

    adc matlab code

    Abstract: matlaB HP16517A AN3495 HP16500C APP3495 MAX1121 MAX1122 MAX1123 MAX1124
    Contextual Info: Maxim > App Notes > BASESTATIONS / WIRELESS INFRASTRUCTURE HIGH-SPEED SIGNAL PROCESSING DIGITAL POTENTIOMETERS Keywords: integral nonlinearity, differential nonlinearity, INL, DNL, analog-to-digital converter, ADC, converter, data record, logic analyzer, data capture, concatenate


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    max1121max1122max1123max1124+10max1213max19541max19542an3495app3495appnote3495adc matlab codematlabhp16517ahp16500c PDF

    Contextual Info: System Generator for DSP Getting Started Guide UG639 v 14.3 October 16, 2012 This document applies to the following software versions: ISE Design Suite 14.3 through 14.6 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development


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    ug639 PDF

    multimedia projects based on matlab

    Abstract: fixed point matlab system generator matlab ise matlab code for FFT 32 point FFT CODING BY VERILOG FOR 8 POINT WITH RADIX 2 E-SYN-0002 XtremeDSP Solution
    Contextual Info: AccelDSP Synthesis Tool User Guide Release 10.1.1 April, 2008 R R Xilinx is disclosing this Document and Intellectual Property hereinafter “the Design” to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished,


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    -dir-0013-dir-0015-dir-0016-dir-5001+13-mat-0008-mat-0301-qor-0400-qtz-0006-qtz-0010-qtz-0011multimedia projects based on matlabfixed point matlabsystem generator matlab isematlab code for fft 32 pointfft coding by verilog for 8 point with radix 2e-syn-0002xtremedsp solution PDF

    UG639

    Contextual Info: System Generator for DSP Getting Started Guide UG639 v 13.1 March 1, 2011 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the


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    ug639 PDF

    matlab code using 64 point radix 8

    Abstract: radix-2 1345-2 radix fht 100
    Contextual Info: HammerCores by Altera White Paper Hadamard Transform Processor Introduction ® The Hammercores by Altera Hadamard Transform Processor core is optimized for the Altera FLEX 10KE, ACEX 1K, and APEX 20K device families. The core is parameterizable and can support a wide range of transform


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    matlab code using 64 point radix 8radix-21345-2radix+1fht 100 PDF

    matlab code for n point DFT using fft

    Abstract: matlab code using 8 point DFT butterfly fft matlab code using 16 point DFT butterfly fft matlab code using 8 point DFT butterfly vhdl code for dFT 32 point vhdl code for FFT 32 point matlab code for FFT 32 point fft dft MATLAB tcl script ModelSim fixed point implementation matlab
    Contextual Info: DFT/IDFT Reference Design Application Note 464 May 2007, version 1.0 Introduction The DFT reference design performs a discrete Fourier transform DFT or an inverse DFT (IDFT) of a complex input sequence and produces a complex output sequence. The reference design performs the functions for either a DFT in the uplink


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    r1-06285246bismatlab code for n point dft using fftmatlab code using 8 point dft butterfly+8fft matlab code using 16 point dft butterflyfft matlab code using 8 point dft butterflyvhdl code for dft 32 pointvhdl code for fft 32 pointmatlab code for fft 32 pointfft dft matlabtcl script modelsimfixed point implementation matlab PDF

    AT 2005B

    Abstract: AT 2005B at 2005b
    Contextual Info: DSP Builder Release Notes Release Notes April 2006, Version 6.0 SP1 These release notes for DSP Builder version 6.0 SP1 contain the following information: • ■ ■ ■ ■ ■ ■ ■ System Requirements System Requirements New Features & Enhancements Errata Fixed in This Release


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    2000/xpat 2005bat 2005b at2005b PDF

    verilog code for cordic algorithm

    Abstract: cordic algorithm code in verilog FIR filter design using cordic algorithm CORDIC adaptive algorithm dpd verilog code for dpd verilog code for cordic altera CORDIC ip verilog code for half subtractor verilog code for cordic algorithm for wireless
    Contextual Info: Digital Predistortion Reference Design Application Note AN-314-1.0 Introduction Power amplifiers PAs for for third-generation (3G) wireless communication systems need high linearity at the PA output, to achieve high adjacent channel leakage ratio (ACLR) and low error vector


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    an-314-1verilog code for cordic algorithmcordic algorithm code in verilogfir filter design using cordic algorithm+7cordicadaptive algorithm dpdverilog code for dpdverilog code for cordicaltera cordic ipverilog code for half subtractorverilog code for cordic algorithm for wireless PDF

    A3PE1500-PQ208

    Abstract: 341a
    Contextual Info: Synplify DSP AE Design Flow Quickstart and Design Tutorial Actel Corporation, Mountain View, CA 94043 2006 Actel Corporation. All rights reserved. Printed in the United States of America Part Number: 50200083-2 Release: November 2007 No part of this document may be copied or reproduced in any form or by any means without prior written


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    a3pe1500-pq208341a PDF

    Contextual Info: Agilent E1432A, E1433B, E1434A VXI Digitizers/Source Product Overview A high-performance system architecture for demanding mechanical, acoustic and electrical data acquisition applications. ● Agilent E1432A 16-channel 51.2 kSa/sec/chan Digitzer plus DSP


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    e1432ae1433be1434a16-channel PDF

    AT 2005B

    Abstract: AT 2005B at 2005b EP2C35 EP2S180
    Contextual Info: DSP Builder Release Notes Release Notes March 2007, Version 7.0 These release notes for DSP Builder version 7.0 contain the following information: • ■ ■ ■ ■ ■ ■ ■ System Requirements System Requirements New Features & Enhancements Errata Fixed in This Release


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    2000/xpat 2005bat 2005b at2005b+2ep2c35ep2s180 PDF

    AT 2005B

    Abstract: AT 2005B at 2005B EP2C35 EP2S180
    Contextual Info: DSP Builder Release Notes Release Notes December 2006, Version 6.1 These release notes for DSP Builder version 6.1 contain the following information: • ■ ■ ■ ■ ■ ■ ■ System Requirements System Requirements New Features & Enhancements Errata Fixed in This Release


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    2000/xpat 2005bat 2005b at2005b+2ep2c35ep2s180 PDF

    LMS matlab

    Abstract: FIR filter matlaB design LMS adaptive filter matlab matlab OIF2003 SDD21 fir filter design ifft transmitter
    Contextual Info: Studies on FIR Filter Pre-Emphasis for High-Speed Backplane Data Transmission Miao Li Department of Electronics Carleton University Ottawa, ON. K1S5B6, Canada Tel: 613 5205754 Email:mili@doe.carleton.ca Yuming Tao Ottawa IC Development ALTERA Corp. Ottawa, ON. K2K3C9 Canada


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    5-10gbs25-umoif2003lms matlab+6fir filter matlab designlms adaptive filter matlabmatlabsdd21fir filter designifft transmitter PDF

    verilog for Twiddle factor

    Abstract: verilog for 8 point fft Radix-3 FFT verilog for 16 point fft fft algorithm verilog an4801 verilog radix 2 fft fft dft MATLAB radix-2 fft verilog dit fft algorithm verilog
    Contextual Info: 1536-Point FFT for 3GPP Long Term Evolution Application Note 480 October 2007, ver. 1.0 Introduction 3GPP Long Term Evolution LTE is an ongoing project to improve the universal mobile telecommunication system (UMTS) standard to handle future requirements of mobile phones. The main targets include higher


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    1536-pointverilog for twiddle factorverilog for 8 point fftradix-3 fft+7verilog for 16 point fftfft algorithm verilogan4801verilog radix 2 fftfft dft matlabradix-2 fft verilogdit fft algorithm verilog PDF