MASTER SSC 1 Search Results

Super10

Abstract: UDE RD1 ST10 SXM 08 rbps2 SXLB
Contextual Info: Super10 STANDARD PERIPHERAL USER’S MANUAL Release 1.2 June 2004 This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Super10 STANDARD PERIPHERAL USER’S MANUAL PREFACE By introducing the ST10 family member Super10, STMicroelectronics is expanding its offer on strategic

CS5571

Abstract: CS5571-ISZ LSB16 MO-150
Contextual Info: 6/25/07 14:12 CS5571 ±2.5 V / 5 V, 100 kSps, 16-bit, High-throughput ∆Σ ADC Features & Description General Description ‰ Single-ended Analog Input The CS5571 is a single-channel, 16-bit analog-to-digital converter capable of 100 kSps conversion rate. The input

siemens C166 instruction set

Abstract: SAB-C165-L25M C165 SAB-C165-LM SAB-C165-LM3V SAF-C165-L25M SAF-C165-LM SAF-C165-LM3V CPU21
Contextual Info: Microcontroller Components Errata Sheet March 30, 2001 / Release 1.0 Device: Stepping Code / Marking: Package: SAB-C165-LM, -LF SAF-C165-LM, -LF SAB-C165-L25M, -L25F SAF-C165-L25M, -L25F SAB-C165-LM3V, -LF3V SAF-C165-LM3V, -LF3V ES-HA, HA P-MQFP-100, P-TQFP-100

AT91SAM7S32

Abstract: AT91SAM7S32-AU-001 PA17 PA18 PA19 PA20 15Two-wire
Contextual Info: Errata • Universal Synchronous Asynchronous Receiver Transmitter USART – Hardware Handshake (21) • Serial Peripheral Interface (SPI) • • • • • • • • • – Pulse Generation on SPCK (20) – MCK/32 Clock Selection (19) Parallel Input/Output Controller (PIO)

74hc595 equivalent

Abstract: CS5102A cdb5101a CS5101A-JP8 CS5101A CS5101A-BP8 MetraByte
Contextual Info: CS5101A CS5102A 16-Bit, 100 kHz / 20 kHz A/D Converters Features Description l Monolithic CMOS A/D Converters The CS5101A and CS5102A are 16-bit monolithic CMOS analog-to-digital converters capable of 100 kHz 5101A and 20 kHz (5102A) throughput. The CS5102A’s low power consumption of 44 mW, coupled

AT91SAM7S128

Abstract: PA31 ATMEl 326 AT91SAM7S128-AU-001 PA17 PA20 PA21
Contextual Info: Errata • Serial Peripheral Interface SPI – MCK/32 Clock Selection (20) • Parallel Input/Output Controller (PIO) • • • • • • • • • – Leakage on PA17 - PA20 (19) – Electrical Characteristics on NRST and PAO (18) – Drive Low NRST, PA0-PA16 and PA21 - PA31 (17)

PEF 7071

Abstract: C166CBC siemens microprocessor c161 C161U siemens b 58 295 bd intel 80 C161 C165 C166 FE4A V24-interface
Contextual Info: L IA T N E ID F N ICs for Communications O Embedded C166 with USB, IOM-2 Interface and HDLC Support C165 UTAH/C161U Version 1.0 C Last modified 12/14/98 Target Specification 12.98 DS 1 C165 UTAH/C161 U CONFIDENTIAL Revision History: Current Version: Version 1.0

AT91SAM7S512

Abstract: K 2611 MOSFET equal 40178 401068 Atmel AT24LC512 EEPROM AT91SAM7S-EK AT91SAM7S256 Atmel 0342 AT91SAM7S128 AT91SAM7S64
Contextual Info: Features • Incorporates the ARM7TDMI ARM® Thumb® Processor • • • • • • • • • • – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – EmbeddedICE In-circuit Emulation, Debug Communication Channel Support

thumb instructions for stepper motor interfacing

Abstract: Cortex A9 instruction set ATSAM3S8BA-MU 0x28AB0A60 11090AS cortex a15 core QFN64 9x9 ATmel cortex a9 microcontroller ARM cortex a15 cpu sdhc sam
Contextual Info: Features • Core • • • • • • • – ARM Cortex®-M3 revision 2.0 running at up to 64 MHz – Memory Protection Unit MPU – Thumb®-2 instruction set Pin-to-pin compatible with AT91SAM7S legacy products (64-pin versions), SAM3S4/2/1 products

AP1651

Abstract: master ssc 1 A166 C161 C161O C166 C16X L166
Contextual Info: Microcontrollers ApNote AP165101 or æ additional file AP165101.EXE available Emulating an asynchronous serial interface ASC via the on-chip synchronous serial interface (SSC) Abstract: The solution presented in this paper and in the attached source files emulates the most

Contextual Info: S i 5 3 119 19-O UTPUT PCI E G EN 3 BUFFER Features   Description The Si53119 is a 19-output, low-power HCSL differential clock buffer that meets all of the performance requirements of the Intel DB1200ZL specification. The device is optimized for distributing refere nce clocks for

C167 AA C5

Abstract: st10 Bootstrap C167 ST10 ST10167 C167 Bootstrap SYSCON external RAM C167 flash programming
Contextual Info: C167 FAMILY PRELIMINARY USER MANUAL C167 FAMILY PRELIMINARY USER MANUAL USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED SGS-THOMSON PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF SGS-THOMSON

str f 6552

Abstract: CV125 IDTCV125 str 6552 CK410M DOT96 LVDS SSC
Contextual Info: IDTCV125 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR DESCRIPTION: FEATURES: IDTCV125 is a 56 pin clock device, incorporating both Intel CK410M and CKSSCD requirements, for Intel advance P4 processors. The CPU output

48MHZ

Abstract: DOT96 IDTCV110L
Contextual Info: IDTCV110L PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR IDTCV110L FEATURES: DESCRIPTION: • One high precision PLL for CPU, SSC, and N programming • One high precision PLL for SRC/PCI/SATA, SSC, and N

Contextual Info: D S99R 124AQ DS99R124AQ 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter Texas In s t r u m e n t s Literature Number: SNLS342 N a tio n a l July1 D S 99R 124A Q Semiconductor 5 - 4 3 M H z 18-bit C o lo r F P D -L in k II to F P D -L in k C o n ve rte r

diode T35 12H

Abstract: PQFP144 ST10 ST10C167 st10 Bootstrap
Contextual Info: ST10C167 16-BIT MCU WITH 32K BYTE ROM • 16 32K Byte ROM 32 16 CPU-Core 16 PEC Internal RAM Watchdog 16 XRAM Interrupt Controller 16 OSC. 8 Port 6 8 Port 5 16 BR G BR G Port 3 15 Port 7 8 August 1999 This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

SLG63103-1

Abstract: 1117 3.3v 318M CK505 ck505-compliant
Contextual Info: SLG63103-1 Media Clock with Differential Memory Clock Output Description • • Low phase noise and wide output frequency range makes the SLG63103-1 a flexible system clock suitable for different types of memory technologies. • SLG63103-1 is CK505 compliant system clock for digital

AT32UC3A0512

Abstract: AT32UC3A0512-ALUT 1px00 AT32UC3A0128-ALUT AT32UC3A1256 AT32UC3A0256 ISO7816 AT32UC3A uC3015 AT32UC3A0256-ALUT
Contextual Info: Features • High Performance, Low Power AVR 32 UC 32-Bit Microcontroller • • • • • • • • • • • • • • • • • • • – Compact Single-cycle RISC Instruction Set Including DSP Instruction Set – Read-Modify-Write Instructions and Atomic Bit Manipulation

CK410B

Abstract: PI6C20400 PI6C20800 PI6C21200 PI6C410B RW1N differential buffer for pci-express
Contextual Info: PI6C21900 PCI Express Gen II1:19 Geared Differential Buffer -17 and 2 Outputs Features Description • Phase jitter filter for PCIe Gen II application PI6C21900 is a PCI Express Gen II compliant, high-speed, low-noise PCI-Express and FBDIMM differential clock buffer designed to be

atmel errata at91rm9200

Abstract: 58a07 6015G AT91RM9200 PA21 AT91RM9200 SDRAM PC638
Contextual Info: Errata • DC Characteristics – Static Current: Static Current Change 43 • AC Characteristics – PLL Frequency Limitation (42) • UHP – No Pulldown on Port 2 Using 208-lead PQFP Package (41) • MultiMedia Card Interface – Data Endianess is Inverted from MCI to MMC or SD Card (40)

SLG84410IE

Abstract: SLG84410 CK410 SLG8
Contextual Info: SLG84410IE Clock Synthesizer for Intel PCI-Express Chipset Features Output Summary • Supports Intel PCI-Epress Chipset CK410 • 2 - differential CPU clock outputs @ 0.7V • Compliance to PCI-Express reference clock specification • 1 - selectable differential CPU/SRC clock output @ 0.7V

atmel 928

Abstract: hsb 772 p atmel sd controller 7816 spi slave AVR32 AC97 AT32AP7002 AVR32 AVR32AP AVR32B avr write read to mmc
Contextual Info: Features • High Performance, Low Power AVR 32 32-Bit Microcontroller • • • • • • • • • • • • • • • • • • – 210 DMIPS throughput at 150 MHz – 16 KB instruction cache and 16 KB data caches – Memory Management Unit enabling use of operating systems

Contextual Info: IDTCV109E CLOCK GENERATOR FOR DESKTOP PC PLATFORMS COMMERCIAL TEMPERATURE RANGE CLOCK GENERATOR FOR DESKTOP PC PLATFORMS DESCRIPTION: FEATURES: • • • • • • • • • • • IDTCV109E IDTCV109E is a 48 pin clock generation device for desktop PC platforms.

CDCE949

Abstract: CDCEL949 TSSOP24
Contextual Info: CDCE949 CDCEL949 www.ti.com SCAS844D – AUGUST 2007 – REVISED MARCH 2010 Programmable 4-PLL VCXO Clock Synthesizer with 1.8V, 2.5V and 3.3V LVCMOS Outputs Check for Samples: CDCE949, CDCEL949 FEATURES • 1 • Member of Programmable Clock Generator Family