MASTER BUS ASI Search Results

DP83932

Abstract: EISA9032 lh 9032 intel 82596 fci dh 22 T35 12H ix031 LA23-LA13 9010 plx LHi 954
Contextual Info: EISA 9032 T •CHNOLOBV^ EISA Bus Master Interface Chip Intel 82596 Mode APRIL 1993 Patent Pending_ Features_ General Description_ • EISA Bus Master Interface Chip containing all The EISA 9032 is an EISA bus master chip which can be

OJP 201

Abstract: T45 12H
Contextual Info: EISA 9032 T•CHNOLOBV^ EISA Bus Master Interface Chip Intel 82596 Mode APRIL 1993 Patent Pending_ Features_ General Description_ • EISA Bus Master Interface Chip containing all The EISA 9032 is an EISA bus master chip which can be

eeprom 24c04

Abstract: 014b signetics 24C04 24CXX 24LC01 24LC04 AN554 PIC16C64 PIC16C71 PIC16C74
Contextual Info: Software Implementation of I2C Bus Master AN554 Software Implementation of I2C Bus Master In most systems the microcontroller is the master and the external peripheral devices are slaves. In these cases this application note can be used to attach I2C slaves to the PIC16CXX the master microcontroller.

93CS56

Abstract: doorbell ID l960 pci9080 9060ES 93C06 NM93CS06 NM93CS46 PCI9060ES doorbell
Contextual Info: PCI 9060ES T e c T T T T S T T ^ T T November 1995 VERSION 1.0 PCI Bus Master Interface Chip for Adapters and Embedded Systems Features General Description PCI Bus Master and Bus Slave transfers up to 132 megabytes/sec supporting three architectures: - PCI Direct Master adapter

PCA9541

Abstract: 4A-23
Contextual Info: PCA9541 2-to-1 I2C master selector with interrupt logic and reset MASTER 0 I2C BUS SDA OFF SCL MASTER 1 I2C BUS INTERRUPT 0 OUT INTERRUPT 1 OUT I2C SLAVE DEVICES INTERRUPT INPUT I2C CONTROLLER RESET INPUT VDD Semiconductors ADDRESS INPUTS GND Features •

PICMG 2.0 R3.0

Abstract: DCA4-4F10 3G8F8-CRM21 IEC60068-2-6 PICMG 2.0 pc to omron plc 3G8F7-CRM21
Contextual Info: New Product CompoNet Master Board for PCI Bus/CompactPCI Bus 3G8F7-CRM21/3G8F8-CRM21 CompoNet Master Board for PC which provides ultra-high speed control • Two type product variation of PCI Bus type and Compact PCI Bus type • Windows-base environment. Compatible with other OS,

pci core

Abstract: Soft Core RTL FIFO synchronous fifo design in verilog
Contextual Info: PCI Peripheral Core PCI ADOUT Register Core Block Diagram PCI Parity Multiplexer Register Master Write FIFO PCI Bus Register Master Read FIFO Master State Machine/ DMA Register Master Request FIFO Output Mux Application Interface PCI I/O Cells ▼ Configuration

h420

Abstract: DS1004 MPC860 0x00034 0X00005
Contextual Info: LatticeSC MPI/System Bus April 2010 Technical Note TN1085 Introduction The embedded system bus on the LatticeSC ties all of the programmable elements together in a bus framework. There are two types of interfaces on the system bus, master and slave. A master interface has the ability to perform

A5S25

Abstract: 0X00003 0X00002 h420 ispLEVER project Navigator 0X00004 DS1004 MPC860 0x0000A TN1080
Contextual Info: LatticeSC MPI/System Bus April 2008 Technical Note TN1085 Introduction The embedded system bus on the LatticeSC ties all of the programmable elements together in a bus framework. There are two types of interfaces on the system bus, master and slave. A master interface has the ability to perform

XAPP1052

Abstract: asus motherboard FPGA based dma controller using vhdl asus motherboard data sheet asus p5b XC5VLX50T-1FFG1136 dell power edge virtex 2 pro XAPP1002 "Asus P5B-VM"
Contextual Info: Application Note: Virtex-5 Family R XAPP1052 v1.1 August 22, 2008 Summary Bus Master DMA Reference Design for the Xilinx Endpoint Block Plus Core for PCI Express Author: Jake Wiltgen This application note discusses how to design and implement a Bus Master Direct Memory

Application Notes

Abstract: AVR32109 Master sequence device I2C TWI AVR32107 AVR32
Contextual Info: AVR32107: Using TWI as a Master on the AVR32 Features - Compatible with Philips' I2C protocol Master transmitter mode Master receiver mode 7-bit slave address – up to 127 devices on the same bus Normal 100kbps and Fast (400kbps) operation Interrupt driven communication

Contextual Info:  Compliant with PCI Local Bus Specification, Revision 2.3  66 MHz performance PCI clock frequency PCI-M64  64-bit datapath 64-bit/66Mhz PCI Master/Target Interface Core  Zero wait states burst mode  Full bus Master/Target functio- nality  Single interrupt support

Contextual Info:  Compliant with PCI Local Bus Specification, Revision 2.3  66 MHz performance PCI clock frequency PCI-M64  64-bit datapath 64-bit/66Mhz PCI Master/Target Interface Core  Zero wait states burst mode  Full bus Master/Target functio- nality  Single interrupt support

MCP2221

Abstract: Controller
Contextual Info: MCP2221 USB 2.0 to I2C/UART Protocol Converter with GPIO Features: I2C/SMBus Universal Serial Bus USB • The Device runs as an I2C Master. The Data to Write/Read on the I2C Bus is conveyed by the USB Interface. • I2C Master - Up to 400 kHz Clock Rate

example ml605

Abstract: XAPP1052 asus motherboard FPGA based dma controller using vhdl virtex-6 ML605 user guide ML605 UCF FILE ML555 xapp1052 document asus p5b sp605
Contextual Info: Application Note: Virtex-6, Virtex-5, Spartan-6 and Spartan-3 FPGA Families Bus Master DMA Performance Demonstration Reference Design for the Xilinx Endpoint PCI Express Solutions XAPP1052 v2.0 November 18, 2009 Summary Author: Jake Wiltgen This application note discusses how to design and implement a Bus Master Direct Memory

XC6SLX9

Abstract: Spartan6 XC6SLX9 XC6SL* MEMORY spartan 3e xc3s500e XC3S500E
Contextual Info: Fully compliant with the PCI Local Bus Specification, Revision 2.3. PCI-M32MF Multi-Function PCI Master/Target Interface Core The PCI-M32MF implements a master/target PCI interface compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates up to 33 MHz 66 MHz

ARM7TDI

Contextual Info: Features • Atmel Advanced System Bus ASB Arbitration • Customized Options – Number of Masters (2 to 7) – Priority of Masters – Possibility of Inserting Master Hand-over Cycle for Each Master • Atmel AMBA Master Compliant • Fully Scan Testable up to 96% Fault Coverage

U10000

Abstract: UUU100 priority arbitration system
Contextual Info: Features • Atmel Advanced System Bus ASB Arbitration • Customized Options – Number of Masters (2 to 7) – Priority of Masters – Possibility of Inserting Master Hand-over Cycle for Each Master • Atmel AMBA Master Compliant • Fully Scan Testable up to 96% Fault Coverage

asus motherboard

Abstract: design of dma controller using vhdl ML605 UCF FILE TLP 3616 XILINX/SPARTAN 3E STARTER BOARD "Asus P5B-VM" XBMD sp605 virtex-6 ML605 user guide virtex ucf file 6
Contextual Info: Application Note: Virtex-6, Virtex-5, Spartan-6 and Spartan-3 FPGA Families Bus Master DMA Performance Demonstration Reference Design for the Xilinx Endpoint PCI Express Solutions XAPP1052 November 4, 2010 Summary Author: Jake Wiltgen and John Ayer This application note discusses how to design and implement a Bus Master Direct Memory

EP201

Abstract: LFX1200B MPC8260 PowerPC 8260
Contextual Info: Product Summary EP201 PowerPC Bus Master FEATURES • Fully supports PowerPC 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260. • Automatic bus arbitration for address bus and data bus based on internal bus request. • Separate address bus and data bus tenure with individual grant signals.

bus arbitration

Abstract: EP201 LFX1200B MPC8260
Contextual Info: Eureka Technology Product Summary EP201 PowerPC Bus Master FEATURES • Fully supports PowerPC 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260. • Automatic bus arbitration for address bus and data bus based on internal bus request. • Separate address bus and data bus tenure with individual grant signals.

24C04 code example assembly

Abstract: 0E-18 24LC04 28AD AN554 24C04 24CXX 24LC01 PIC16C64 PIC16C71
Contextual Info: M AN554 Software Implementation of I2C Bus Master Author: Amar Palacherla Microchip Technology Inc. INTRODUCTION This application note describes the software implementation of I2C interface routines for the PIC16CXXX family of devices. Only the master mode of

24C04 code example assembly

Abstract: program eeprom 24c04 6 how to reset 24lC04 TELETEXT TRANSMITTER 2817 EEPROM TM 1628 driver display 0E-18 eeprom 24c04 eeprom 2817 how to reset 24C04
Contextual Info: M AN554 Software Implementation of I2C Bus Master Author: Amar Palacherla Microchip Technology Inc. INTRODUCTION This application note describes the software implementation of I2C interface routines for the PIC16CXXX family of devices. Only the master mode of

bus arbitration

Abstract: APA150-STD EP201 MPC8260
Contextual Info: Eureka Technology Product Summary EP201 PowerPC Bus Master FEATURES • Fully supports PowerPC 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260. • Automatic bus arbitration for address bus and data bus based on internal bus request. • Separate address bus and data bus tenure with individual grant signals.