MACH111 PLCC Search Results

BP1148

Abstract: MACH111-20JC MACH110 MACH210 MACH215 PAL22V10
Contextual Info: FINAL COM’L: -5/7.5/10/12/15/20 IND: -7.5/10/12/14/18/24 MACH111 Family High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 44 Pins ■ Programmable power-down mode ■ 32 Macrocells ■ 32 Outputs ■ 5 ns tPD ■ 32 Flip-flops; 4 clock choices

Contextual Info: FINAL BEYO N D PERFO RM A N CE COM’L: -5/7/10/12/15 IND: -7/10/12/14/18 M A C H 1 11 - 5 /7 /1 0 /1 2 /1 5 High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ 44 Pins in PLCC and TQFP

MACH111

Abstract: HP3070 PALCE22V10 mach111 plcc MACHpro
Contextual Info: 1 FINAL MACH 1 & 2 FAMILIES COM’L: -5/7/10/12/15 IND: -7/10/12/14/18 High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ◆ 44 Pins in PLCC and TQFP ◆ 32 Macrocells ◆ 5 ns tPD Commercial, 7.5 ns tPD Industrial ◆ 182 MHz fCNT ◆ 32 I/Os; 4 dedicated inputs/clocks; 2 dedicated inputs

Contextual Info: V AN A — / FINAL ▼ M A C H 1 1 1 -5 /7 /1 0 /1 2 /1 5 N A M D T I S C O M 'L :-5/7/10/12/15 IN D :-7/10/12/14/18 High-Performance EE CMOS Programmable Logic C O M P A N Y DISTINCTIVE CHARACTERISTICS ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ 44 Pins in PLCC and TQFP

HP3070

Abstract: PALCE22V10
Contextual Info: 1 FINAL MACH 1 & 2 FAMILIES COM’L: -5/7/10/12/15 IND: -7/10/12/14/18 High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ◆ 44 Pins in PLCC and TQFP ◆ 32 Macrocells ◆ 5 ns tPD Commercial, 7.5 ns tPD Industrial ◆ 182 MHz fCNT ◆ 32 I/Os; 4 dedicated inputs/clocks; 2 dedicated inputs

STR F 6168

Abstract: str 6168 teradyne flex tester Vantis macro library STR F 8033 MACH111 12JC 14JI str f 6168 data sheet HI-LO ALL-07 STR F 6168 31 v power teradyne lasar
Contextual Info: FINAL COM’L: -5/7/10/12/15 IND: -7/10/12/14/18 MACH 111-5/7/10/12/15 High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ◆ 44 Pins in PLCC and TQFP ◆ 32 Macrocells ◆ 5 ns tPD Commercial, 7.5 ns tPD Industrial ◆ 182 MHz fCNT ◆ 32 I/Os; 4 dedicated inputs/clocks; 2 dedicated inputs

mach 1 to 5 from amd

Abstract: pal programmer schematic mach 1 to 5 family amd mach 1 family amd Simulating MACH Designs MACH110 "pin compatible" MACH Programmer MACH231
Contextual Info: a AdVMicro CONDENSED MACH 1 and 2 Device Families High-Density EE CMOS Programmable Logic Devices DISTINCTIVE CHARACTERISTICS • High-performance, high-density, electrically-erasable CMOS PLD families ■ 900 to 3600 PLD gates ■ 44 to 84 pins in cost-effective PLCC and TQFP

MACH131SP-5YC-7YI

Abstract: 14051k MACH Programmer PAL 007 PAL 007 A Pal programming MACH111SP MACH211SP mach210 die Vantis macro gates
Contextual Info: MACH 1 and 2 CPLD Families High-Performance EE CMOS Programmable Logic FEATURES ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ High-performance electrically-erasable CMOS PLD families 32 to 128 macrocells 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages

gg3b

Contextual Info: FINAL COM’L: -5/7.5/10/12/15/20 a Advanced Micro Devices M A C H 1 11 -5 /7 / 1 0 / 1 2 / 1 5 /2 0 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 44 Pins ■ Programmable power-down mode ■ 32 Macrocells ■ 32 Outputs ■ 5 ns tpD

mach210 die

Abstract: AP-Q mach schematic mach 1 family MACH Programmer PAL 007 PAL 007 A PAL 007 c Pal programming MACH111SP
Contextual Info: MACH 1 and 2 CPLD Families High-Performance EE CMOS Programmable Logic FEATURES ◆ ◆ ◆ ◆ ◆ ◆ ◆ High-performance electrically-erasable CMOS PLD families 32 to 128 macrocells 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages SpeedLocking – guaranteed fixed timing up to 16 product terms

MACH211SP

Abstract: mach schematic MACH111SP
Contextual Info: MACH 1 and 2 CPLD Families High-Performance EE CMOS Programmable Logic FEATURES ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ High-performance electrically-erasable CMOS PLD families 32 to 128 macrocells 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages

Contextual Info: FIN AL M A C H 1 1 1 COM’L: -5/7.5/10/12/15/20 IND: -7.5/10/12/14/18/24 AM D£t F a m ily High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 44 Pins ■ Programmable power-down mode ■ 32 Macrocells ■ 32 Outputs ■ 5 ns tPD ■ 32 Flip-flops; 4 clock choices

Contextual Info: PRELIMINARY M ACH COM’L: -7/10/12/15/20 a 1 1 1 - 7 /1 0 /1 2 /1 5 /2 0 Advanced Micro Devices High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 44 Pins ■ 32 Outputs ■ 32 Macrocells ■ 32 Flip-flops; 4 clock choices ■ 7.5 ns tpD

sp9648

Abstract: ci pal 014
Contextual Info: V A N B EY O N D P ER F O R M A N C E MACH 1 and 2 CPLD Families High-Performance EE CMOS Programmable Logic FEATURES High-performance electrically-erasable CMOS PLD families 32 to 128 macrocells 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages

Contextual Info: MACH 1 and 2 CPLD Families BEYOND PERFORM ANCE H igh-Perform ance EE C M O S P rogram m able Logic FEATURES ♦ ♦ ♦ ♦ ♦ ♦ — Programmable polarity — Registered or com binatorial outputs — Internal and I/O feedback paths — D-type or T-type flip-flops

Contextual Info: MACH 1 and 2 CPLD Families BEY O N D PER FO RM AN C E High-Performance EE CMOS Programmable Logic FEATURES — — — — — — — Programmable polarity Registered or com binatorial outputs Internal and I/O feedback paths D-type or T-type flip-flops O utput Enables

Contextual Info: CO M ’L: -5/7.5/10/12/15/20 M A C H 1 11 -5 /7 /1 0 /1 2 /1 5 /2 0 High-Density EE CMOS Programmable Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 44 Pins ■ Program m able power-down mode ■ 32 M acrocells ■ ■ 5 ns tpD ■ 32 Flip-flops; 4 clock choices

ulc xc3030

Abstract: PQFP 176 Xilinx XC3090 altera EP300 EPM7128 Temic ulc xc3030 EPM7128 PLCC PLSI2032 Actel A1020 PLUS405
Contextual Info: ULC Reference Guide This reference guide lists most devices available for conversion. This list is not exhaustive, as new devices are added regularly. Additional devices not shown in this list may also be supported. Updated versions are available on the TEMIC web site. Check with factory if

MACH211-14

Abstract: HP3070 PALCE22V10 19601C-1
Contextual Info: MACH 1 & 2 FAMILIES 1 FINAL COM’L: -7/10/12/15 IND: -10/12/14/18 High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ◆ 44 Pins in PLCC and TQFP ◆ 64 Macrocells ◆ 7.5 ns tPD Commercial, 10 ns tPD Industrial ◆ 133 MHz fCNT ◆ 32 I/Os; 2 dedicated inputs; 4 dedicated inputs/clocks

PAL22V16

Abstract: MACH110 MACH210 MACH215 PAL22V10
Contextual Info: FINAL COM’L: -12/15/20 IND: -14/18/24 MACH110-12/15/20 Lattice/Vantis High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 44 Pins ■ 32 Outputs ■ 32 Macrocells ■ 32 Flip-flops; 2 clock choices ■ 12 ns tPD Commercial 14 ns tPD Industrial

Contextual Info: FINAL COM’L: -12/15/20 IND: -14/18/24 Lattice/Vantis M A C H 1 1 0 -1 2 / 1 5 /2 0 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 44 Pins ■ 32 Outputs ■ 32 Macrocells ■ 32 Flip-flops; 2 clock choices ■ 12 ns tpD Commercial

PAL22V16

Abstract: MACH110 MACH210 MACH215 PAL22V10 AIR33
Contextual Info: FINAL COM’L: -12/15/20 IND: -14/18/24 MACH110-12/15/20 Lattice Semiconductor High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 44 Pins ■ 32 Outputs ■ 32 Macrocells ■ 32 Flip-flops; 2 clock choices ■ 12 ns tPD Commercial 14 ns tPD Industrial

MACH111SP

Abstract: HP3070 MACH211SP PALCE22V10
Contextual Info: 1 FINAL MACH 1 & 2 FAMILIES COM’L: -5/7/10/12/15 IND: -7/10/12/14/18 MACH 1 & 2 Families MACH111SP-5/7/10/12/15 High-Performance EE CMOS In-System Programmable Logic DISTINCTIVE CHARACTERISTICS ◆ JTAG-Compatible, 5-V in-system programming ◆ 44 Pins in PLCC and TQFP

Contextual Info: FINAL C O M 'L : - 7 /1 0 /1 2 /1 5 IN D : -1 0 /1 2 /1 4 /1 8 M A C H 2 1 1 -7 /1 0 /1 2 /1 5 V A N A N A M D T I S High-Performance EE CMOS Programmable Logic C O M P A N Y DISTINCTIVE CHARACTERISTICS ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ 44 Pins in PLCC and TQFP