M-BUS MASTER Search Results

74S245

Abstract: pin configuration 74LS32 74LS32 pin configuration 74LS764
Contextual Info: SCB68175 Signetics Bus Controller Preliminary Specification Microprocessor Products PIN CONFIGURATION DESCRIPTION FEATURES The Signetics SCB68175/8X821 Bus Controller is a high-speed bus requester and timing generator designed to inter­ face a local m aster typically, a m icro­

MACH465

Abstract: 85C30 MACH465-12 EZ-030 AM29030 D1667 29030 27C010 MACH220 MAX232
Contextual Info: Using a PC I Bus as the I /O Bus on an Am29030/040 M icroprocessor Design Application Note This application note describes how the Peripheral Component Interconnect (PCI) bus can be used as the I/O bus portion on a two-bus microcontroller design. Additionally, one

sony tv circuit diagram

Abstract: video signal circuit diagram tv sony diagram tv sony AUD101 CXA1114M CXA1114P sony tv diagram AUD10 CXA1434P sony TV circuits
Contextual Info: SONY CXA1114P/M/CXA1434P Audio Video Switch Compatible with l2C Bus Description The C X A 1114P and CXA1434P are bipolar ICs developed as audio video switches for the l2C bus. CXA1114P CXA1434P 28pin DIP Plastic CXA1114M 28pin SOP (Plastic) Features • Serial control through l2C bus

T7026

Contextual Info: HIGH-SPEED 16K X 16 DUAL-PORT STATIC RAM IDT7026S/L Features * * * * plexed bus compatibility IDT7026 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one d e v ic e _ ♦ M/S = H for BUSY output flag on Master,

PEC 648

Abstract: C1544 C2048 MH89750
Contextual Info: MH89750 T1 Framer & Interface ST-BUS FAM ILY MITEL Features m 9161-002-020-NA iM '>»»» 11 1 »!« ISSUE 4 lliilltI I December 1987 Pin Connections • MITEL ST-BUS compatible • Interface between a 2048 kbit/s, ST-BUS , serial data stream and a bidirectional DS1 link

BSW 002 2nd year date sheet

Abstract: HB52A48DB-10 HB52A48DB-10L HB52A88DC-10L Hitachi DSA00196 Nippon capacitors
Contextual Info: HB52A48DB Series, HB52A88DC Series HB52A48DB 32 MB Unbuffered SDRAM S.O.DIMM 4-Mword x 64-bit, 66 MHz Memory Bus, 1-Bank Module 4 pcs of 4 M × 16 components HB52A88DC 64 MB Unbuffered SDRAM S.O.DIMM 8-Mword × 64-bit, 66 MHz Memory Bus, 2-Bank Module (8 pcs of 4 M × 16 components)

Contextual Info: L O O iO L53C80 SCSI Bus Controller DEVICES INCORPORATED FEA TU RES □ Asynchronous Transfer Rate U p to 4 M bytes/sec □ Low Pow er CM O S Technology □ Replaces N C R 53C80/ 53C80-40 and A M D Am53C80 □ On-Chip SC SI Bus D rivers □ Supports A rbitration, Selection/

Contextual Info: HIGH-SPEED 16Kx 16 DUAL-PORT STATIC RAM IDT7026S/L Integrated D e vic e Techn olo gy, Inc. multiplexed bus compatibility IDT7026 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device M/S = H for B U S Y output flag on Master,

HB52E88EM-D

Abstract: HB52E88EM-B6D hb52e168en-b6d HB52E88EM Hitachi DSA00196 Nippon capacitors
Contextual Info: HB52E88EM-D, HB52E89EM-D, HB52E168EN-D, HB52E169EN-D 64 MB Unbuffered SDRAM DIMM, 100 MHz Memory Bus HB52E88EM 8-Mword x 64-bit, 1-Bank Module (8 pcs of 8 M × 8 Components) (HB52E89EM) 8-Mword × 72-bit, 1-Bank Module (9 pcs of 8 M × 8 Components) 128 MB Unbuffered SDRAM DIMM, 100 MHz Memory Bus

Z684

Abstract: MSM13R0000 MSM98R000 pbeb Signal Path Designer Z684-PCI s/z684 bridge
Contextual Info: Z684 PCI Bus Controller 0.5µ m Technology Mega Macrocell DESCRIPTION The PCI Bus Controller Mega Macrocell is a featured element in OKI’s 0.5µm Sea of Gates SOG and Customer Structured Array (CSA) families. Designers can significantly reduce design and simulation effort

Contextual Info: D M A C O N TR O LLE R 8.1 AMDÌ1 O V E R V IE W Direct memory access DMA permits the transfer of data between memory and peripherals without CPU involvement. With DMA transfers, the DMA controller becomes the bus master. The arbitration for the bus is internal to the processor and is not visible externally. When

NCR53C80

Abstract: L53C80PC
Contextual Info: L5380/L53C80 CMOS SCSI Bus Controller Features Description □ Asyncronous transfer rate up to 4 M bytes/sec The L 5380/ L53C80 are very high per­ formance CMOS controllers which support the physical layer of the SCSI Small Computer System Interface bus as defined by the ANSI X3T9.2

Contextual Info: CMOS Bus Matching SyncFlFO 256 x 36, 512 x 36, 1024 x 36 IJ d t PRELIMINARY ¡¡£¡^23623 IDT723643 Integrated Device Technology, Inc. FEATURES: Big- or Little-Endian form at for w ord and byte bus sizes M aster Reset clears data and configures FIFO, Partial

Contextual Info: PRELIMINARY A m 1 8 6 “ E R a n d A M D ÎI A m 1 8 8 'E R High-Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers with RAM DISTINCTIVE CHARACTERISTICS • E86 family 80C186- and 80C188-compatible m icrocontrollers with enhanced bus interface

6 pins IC cbe

Abstract: irca
Contextual Info: S VlïlBl OS D a ta S h eet SYMI3FW600 PCI to IEEE-1394 Host Bus Interface T he SYM13FW600 chip uses the Link Layer protocol o f the IEEE-1394 serial bus. It also provides direct m em o ry access DM A engines for h igh-perform ance data transfer an d a P eripheral

SC11017CN

Abstract: sim 300 modem at commands set SC11017 SC11017CV 74LS306 SC11014
Contextual Info: SC11017 Enhanced Parallel Bus Modem Controller SIERRA SEMICONDUCTOR □ □ Direct interface to SC11004, S C I 1014 and S C I 1015 single chip m odem s Built-in U A RT □ □ □ Com plete "A T " comm and set in firm w are Direct IBM PC bus interface 28-pin D IP or PLCC package

Contextual Info: GEC PLESSEY I S E~~M I C O N D U C T O R S I 3091-1.3 November 1991 C T 1 602/10 MIL-STD-1553B REMOTE TERMINAL, BUS CONTROLLER OR PASSIVE MONITOR HYBRIDS The CT1602/CT1610 design incorporates five LSI chips that accomplish the dual redundant MIL-STD1553B Remote Terminal and/or Bus Controller Protocol Functions. Buffering has

Cb636

Abstract: y635 yb4 bridge diode gamma ram table Y636 itu 656 vga converter yb6 bridge diode CS7615 CS7665 CS7665-KQ
Contextual Info: CS7665 Digital Color-Space Processor for CCD Cameras Features Description l ITU-601 Compliant Image Formatting l ITU-656 and SMPTE-125/M Transport l Provides Separate HREF and VREF or alternately VSYNC Signals l I2C Control Interface l Limited Secondary I2C Bus Master

Contextual Info: intei A D W M C B O M IF Û fô G M T tM M82370 INTEGRATED SYSTEM PERIPHERAL Programmable Walt State Generator — 0 to 15 Wait States Pipelined — 1 to 16 Wait States Non-Pipelined High Performance 32-Blt DMA Controller for 16-Bit Bus — 16 MBytes/Sec Maximum Data

T8972

Abstract: MT8972AE
Contextual Info: MITEL 3SE SEMI CONDUCTOR D • b2M^37D 0 0 D b b 3 4 T « M IT C MT8972 Digital Network Interface Circuit IS 0 2-C M 0 S ST-BUS F A M IL Y M ITEL* ~ ~ r- ' ISSUE 2 9161-002-12S-NA Features • • • • • • • • • Full duplex transmission over a single twisted pair

74LS245 buffer ic

Contextual Info: A SC11027 Parallel Bus Modem Controller V SIERRA SEMICONDUCTOR □ □ 2 8 -P IN D IP PA CK A G E □ □ □ □ Auto power down Built-in UART Direct IBM PC XT bus interface 28-pin DIP or PLCC package SC11027CV G E N ER A L D E S C R IP T IO N The SC11027 M odem Interface

16c57

Abstract: adb 0702 AN591 PIC16C57 062-2012-A APPLE* adb macintosh 16c56
Contextual Info: M Author: AN591 Apple Desktop Bus ADB EXPLANATION OF ADB TECHNOLOGY Rob McCall WFT Electronics Gus Calabrese Dave Evink Curt Apperson WFT Electronics Support: ADB is an asynchronous pulse-width communication protocol supporting a limited number of devices. All

Contextual Info: $ 25AA320 M ic r o c h ip ,T M 32K 1.8V SPI Bus Serial EEPROM PACKAGE TYPES FEATURES • SPI modes 0,0 and 1,1 • 3.0 MHz Clock Rate • Single supply with Programming Operation down to 1.8V • Low Power CMOS Technology - Max Write Current: 5.0 mA - Read Current: 1.0 mA@ 5.5V 3 Mhz

Ba 33 bco

Contextual Info: Direct RDRAM RAMBUS TM 32/36-M bit 256K x16/18x8d ADVANCE INFORMATION O verview The R am bus Direct RDRAM is a general p u rp o se high-perform ance m em ory device suitable for use in a broad range of applications including com puter mem ory, graphics, video, an d any other application