LSC 117 Search Results

AG1171S

Abstract: SLIC AN2120 ag1171 Ag2120S
Contextual Info: AN2120-25: Dual Layout of Ag2120S & Ag1171S COIC connections are shown in brackets [ ] RB RC RD Pin Outs 1171S SLIC 2120S COIC RING [RING] TIP [TIP] F/R [Cathode] RM [Anode] SHK [Gate] - [Dmb] - [Dma] - - - - - - - - - [LC] Vin [Vin] Vout [Vout] - [LSC] GPWR

LS7261/LS7262

Contextual Info: _ LSI COMPUTER SYSTEMS 54E D LSI/CSI sis- 53D4b0b Q00CH32 blO LSC T 'S X - /J’-02s- LS7260/LS7261 LS7262 Manufacturers of Custom and Standard L S I Circuits 1235 Walt Whitman Road, Melville, N Y 11747-3086 • Tel.: 516 271-0400 • Fax: (516) 271-0405

Contextual Info: 2 lSC- RELEASED FOR PUBLICATION THIS DRAWING IS UNPUBLISHED. c COPYRIGHT — BY FTTT REVISIONS be ie — P LTR 5 a TE DESCRIPTION D1 REVISED P E R ECO-11-005033 2APR11 DWN APVD RK ' H M R _ I_ ; D D ±0. 4 Z>^ 7 ± 0.4 11.8 _ El fcfi(CIRCUT NO * r -V tr

SLIC and TIP and RING

Abstract: Ag2120S AG1170 RM 1206 1170s AN2120 TPP25011 Ag1170S
Contextual Info: Dual Layout of Ag2120S & Ag1170S COIC connections and components are shown in brackets [ ] [ZT] [ZC] [ZB] Pin Outs 1170S SLIC 2120S COIC RING [RING] TIP [TIP] F/R [Cathode] RM [Anode] SHK [Gate] ZT1 [DMB] ZT2 [DMB] - - - - - - - - ZB [LC] VIN [VIN] VOUT [VOUT]

2120D

Abstract: 2120d ic AG2120d ring ic SLIC and TIP and RING 13VOUT AG2120d vin AN2120 iC-nc 16C-B
Contextual Info: Dual Layout of Ag2120D & Ag1170D COIC connections are shown in brackets [ ] RB RC RD Pin Outs 1170D SLIC 2120D COIC TIP [TIP] RING [RING] IC NC [Cathode] PD [Anode] NC [Dma] NC [Dmb] RM [Gate] GNDA [GNDA] VA [Vcc] ZT2 [ZT2] ZT1 [ZT1] Zb [Zb] Vin [Vin] NC

LTP75N08

Abstract: ltp*75n08 LTP75N08P 1000 V N-channel mosfet 100A Mosfet
Contextual Info: LTP75N08P N-Channel 80V Power MOSFET Features: Avalanche Rugged Technology Rugged Gate Oxide Technology High di/dt Capability Improved Gate Charge Application BVDSS = 80 V, Switching DC-DC converter and DC motor control RDS ON = 9.5 mΩ, Typ = 8.5 mΩ

Contextual Info: ispLSI 3192 to 6192 Design Conversion 3. Only 96 I/O pins are available to connect module only interface signals. Introduction With the introduction of the ispLSI 6192, pDS® 3.0 software was also introduced to support the full capability of the device architecture. As an interim solution before

traffic light control verilog

Abstract: lat_vhd jk FLIPFLOP SCHEMATIC
Contextual Info: VHDL and Verilog Simulation User Manual Version 5.1 Technical Support Line: 1- 800-LATTICE or 408 428-6414 pDS1131-UM Rev 5.1.1 Copyright This document may not, in whole or part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine-readable form without

LTP75N08

Abstract: ltp*75n08 LTP75N08P lsc 117
Contextual Info: LTP75N08P N-Channel 80V Power MOSFET Features: Avalanche Rugged Technology Rugged Gate Oxide Technology High di/dt Capability Improved Gate Charge Application BVDSS = 80 V, Switching DC-DC converter and DC motor control RDS ON = 9.5 mΩ, Typ = 8.5 mΩ

Contextual Info: TM TM ispGDX and ispGDS Architectural Description combinatorial outputs. Each I/O cell has individual, programmable tri-state control OE , register or latch clock, (CLK), and programmable polarity. The OE control for each I/O pin is independent and may be driven via the

IO64

Abstract: speed performance of Lattice - PLSI Architecture LATTICE 3000 family architecture
Contextual Info: 3000 Family Architectural Description tectural differences: Boundary Scan, Megablock and GLB structure, Global clock structure, and I/O cell structure. A functional block diagram of the ispLSI 3256 device is shown in Figure 1. The architectural differences are

IO64

Abstract: pin diagram of 8-1 multiplexer design logic
Contextual Info: 3000 Family Architectural Description ences: Boundary Scan, Megablock and GLB structure, Global clock structure, and I/O cell structure. A functional block diagram of the ispLSI 3256A device is shown in Figure 1. The architectural differences are described in

Contextual Info: GAL26CLV12 Lattice Low Voltage E2CMOS PLD Generic Array Logic Semiconductor Corporation FUNCTIONAL BLOCK DIAGRAM FEATURES • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 5 ns Maximum Propagation Delay — Fmax = 200 MHz — 3.5 ns Maximum from Clock Input to Data Output

traffic light control verilog

Abstract: ispLSI2032 cadence leapfrog lat_vhd traffic light controller vhdl 2032E pack1076 expt1076
Contextual Info: VHDL and Verilog Simulation User Manual Version 7.2 Technical Support Line: 1- 800-LATTICE or 408 428-6414 pDS1131-UM Rev 7.2.1 Copyright This document may not, in whole or part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine-readable form without

26CV12

Abstract: GAL26CLV12 GAL26CLV12D-5LJ GAL26CLV12D-7LJ GAL Development Tools
Contextual Info: GAL26CLV12 Low Voltage E2CMOS PLD Generic Array Logic FUNCTIONAL BLOCK DIAGRAM FEATURES 2 • HIGH PERFORMANCE E CMOS TECHNOLOGY — 5 ns Maximum Propagation Delay — Fmax = 200 MHz — 3.5 ns Maximum from Clock Input to Data Output — UltraMOS® Advanced CMOS Technology

1048E

Abstract: 1048E-50 NS-344
Contextual Info: ® ispLSI and pLSI 1048E High-Density Programmable Logic • ispLSI and pLSI DEVELOPMENT TOOLS pDS® Software — Easy to Use PC Windows Interface — Boolean Logic Compiler — Manual Partitioning — Automatic Place and Route — Static Timing Table

2096-80LTI

Abstract: PC 88
Contextual Info: ispLSI and pLSI 2096 ® High Density Programmable Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — — — — — — — fmax = 125 MHz Maximum Operating Frequency tpd = 7.5 ns Propagation Delay

Contextual Info: GAL16LV8ZD Low Voltage, Zero Power E2CMOS PLD Generic Array Logic ; Semiconductor I Corporation F eatures - 3.3V LOW VOLTAGE, ZERO POWER OPERATION — JEDEC Compatible 3.3V Interface Standard — Interfaces with Standard 5V TTL Devices — 50|iA Typical Standby Current 10tyiA Max.

GAL Development Tools

Contextual Info: ispLSI 2096V 3.3V High-Density Programmable Logic Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC • 3.3V LOW VOLTAGE 2096 ARCHITECTURE — Interfaces with Standard 5V TTL Devices — Fuse Map Compatible with 5V ispLSI 2096 • HIGH PERFORMANCE E2CMOS® TECHNOLOGY

lsc 3120

Abstract: 26CV12 GAL26CV12 GAL26CV12B-10LP GAL26CV12C-10LJ GAL26CV12C-10LP GAL26CV12C-7LJ GAL26CV12C-7LP gal programming 22v10
Contextual Info: Specifications GAL26CV12 GAL26CV12 High Performance E2CMOS PLD Generic Array Logic FUNCTIONAL BLOCK DIAGRAM FEATURES • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 7.5 ns Maximum Propagation Delay — Fmax = 142.8 MHz — 4.5ns Maximum from Clock Input to Data Output

PLSI-2064-80LJ

Abstract: ispLSI 2064-80LT isplsi2064 isplsi device layout
Contextual Info: ispLSI and pLSI 2064 ® High Density Programmable Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC Input Bus — 2000 PLD Gates — 64 I/O Pins, Four Dedicated Inputs — 64 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

Contextual Info: PRELIMINARY MX98746 100 BASE-TX/FX 5-PORT CLASSII REPEATER CONTROLLER 1.0 FEATURES • S eparate ja b b e r and partition state m achines fo re a c h port • O n-chip e la sticity buffer fo r PHY signal re-tim ing to the M X 98746 clo ck source •C o n te n ts of internal register loaded from EEPRO M

LSC 132

Contextual Info: ispLSI and pLSI 3256A ® High Density Programmable Logic • HIGH-PERFORMANCE E CMOS TECHNOLOGY — fmax = 90 MHz Maximum Operating Frequency — tpd = 12 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable

0294B

Abstract: 1048-70L
Contextual Info: Specifications ispLSI and pLSI 1048 ® ispLSI and pLSI 1048 High-Density Programmable Logic Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 8000 PLD Gates — 96 I/O Pins, Ten Dedicated Inputs — 288 Registers — High-Speed Global Interconnects