LS112A Search Results

dm74 Series

Abstract: 63821 54LS112 54LS112DMQB 54LS112FMQB DM54LS112AJ DM54LS112AW DM74 DM74LS112AN LS112AM
Contextual Info: LS112A National Semiconductor 54LS112/LS112A/LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and

Contextual Info: LS112A National Semiconductor 54LS112/LS112A/LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the

SN74LS112

Abstract: SN54LS112A SN54S112 SN74LS112A SN74S112A SN54L5112A 5S012
Contextual Info: LS112A, SN54S112, SN74 LS112A , SN74 S 112 A D U A L J-K NE GAT IVE EDGE-TRIGGERED FLIP FLO P S WITH PR ESE T AN D CLEA R SDLS011 D 2 6 6 1 , APRIL 1 9 8 2 —REVISED M A R C H 1 9 8 8 • Fully Buffered to Offer Maximum Isolation from External Disturbance

rdn 100 n 20 550

Abstract: LS112AN MS-012-AB 74ALS 74ALS112A N74ALS112AD N74ALS112AN SOL-24 55120 LS112AD
Contextual Info: S ig n etics 7 4 LS112A F lip -F lo p Dual J-K Negative Edge-triggered Flip-Flop Preliminary Specification ALS Products DESCRIPTION The 74A LS112A, Dual N e g a tiv e Edge- T r ig g e r e d J K -T y p e F lip -F lo p , fe a tu r e s in d i­ v id u a l J, K, C lo c k C P n , S e t ( S D) a n d R e s e t

Contextual Info: LS112A, LS112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FUP-FLOPS WITH CLEAR AND PRESET 02661, A PRIL 1982 - REVISED MAY 1986 • Fully Buffered to Offer Maximum Isolation from External Disturbance • Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers,

74HC4096

Abstract: EQUIVALENT TIMER IC WITH CD 4060 rs flip-flop IC 7400 C4050A shiftregister PIPO C148A LS 7476 L1AA C4051A LS294
Contextual Info: Selection Guide C2MOS Logic TC74HC/HCT Series 2. High Speed CMOS Selection Guide GATE NAND HCOOA NOR AND OR INVERTER, BUFFER EXCLUSIVE OR/NOR SC HM ITT TRIGGER HC02A HC08A H C31A H C04A H C86A H C14A H C51A H C4049A M ULTI FUNCTION LEVEL SHIFTER HCTOOA HCT02A

TDA0161 equivalent

Abstract: 1N3393 BDX54F equivalent byt301000 bux transient voltage suppressor ST90R9 ua776mh sgs 2n3055 Transistor morocco mje13007 inmos transputer reference manual
Contextual Info: SHORTFORM 1995 NOVEMBER 1994 USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED SGS-THOMSON PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF SGS-THOMSON Microelectronics. As used herein:

Contextual Info: SG60R4 Schottky TTL • Over 180 LS Devices • ALS • FAST TOTAL TTL COMMITMENT «TOTAL • TTL Compatible Macrocell Arrays • RAMs • PROMs General Information TTL in Perspective proved speed — p o w e r product co m p ared to LS as a result o f ad vanced M O S A IC oxide isolated processing.

SN74ALS123

Abstract: SN7401 74LS424 54175 SN74298 SN74265 SN74LS630 SN74LS69 National Semiconductor Linear Data Book Transistor AF 138
Contextual Info: INDEX • FUNCTIONAL SELECTION GUIDE • NUMERICAL FUNCTION INTERCHANGEABILITY GUIDE GENERAL INFORMATION AND EXPLANATION OF NEW LOGIC SYMBOLS ORDERING INSTRUCTIONS AND MECHANICAL DATA 54/74 SERIES OF COMPATIBLE TTL CIRCUITS • PIN OUT DIAGRAMS 54/74 FAMILY SSI CIRCUITS

mc68701 probug

Abstract: MC144100 M68KVM02 user manual m6809 EXORCISER motorola MC146805G2 MC1468705G2 AN/mc68701 probug
Contextual Info: Motorola’s Microcomputer Families i Reliability Data Sheets Mechanical Data E Technical Training Memory Products Logic and Special Function Products Development Systems and Board-Level Products E M motorola MICROCOMPUTERS Prepared by Technical Information Center

0PIC

Abstract: LS66 SN74L30 84LS 64LS 84ls AX-2016 MAX2719 hy74 L8128A SN7463
Contextual Info: V 84 F A M IL Y S E R IE S 54 S E R IE S M L S S E R IE S B4S S E R IE S 74 S E R IE S 54H S E R IE S 74H S E R IE S 5 4 L 74 F A M IL Y S E R IE S 7 4 L S E R IE S 7 4 LS S E R IE S 74S *00. *04, *H 0 0 ,1404. *L00, 'U M , XSOO, *100, *S04, '10. *20, *30

LS112AM

Abstract: 74AS112 AX2022
Contextual Info: TYPES LS112A, SN54AS112, LS112A, SN74AS112 DUAL J K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET 0 2 6 6 1 , APRIL 1 9 8 2 —REVISED DECEMBER 1 9 8 3 Fully Buffered to O ffer Maxim um Isolation from External Disturbance J PACKAGE N PACKAGE

54s112

Abstract: 74LS112A 74S112
Contextual Info: LS112A, SN54S112, LS112A. SN74S112A DUAL J K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR _ Fully Buffered to Offer Maximum Isolation from External Disturbance • D 2 6 6 1 . A P R IL 1 9 8 2 - R E V I S E D M A R C H 1 9 8 8

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) JM38510/07102BEA ACTIVE CDIP

74AS112

Abstract: LS112AM
Contextual Info: TYPES LS112A, SN54AS112, LS112A, SN74AS112 DUAL J K NEGATIVE EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET D 2 6 6 1 , A P R IL 1 9 8 2 - R E V I S E D D E C E M B E R 1 9 8 3 • Fully Buffered to Offer Maximum Isolation from External Disturbance

ic 74 LS 138 DECODER

Abstract: Alu 181 8 bit bcd adder/subtractor f245 motorola lal 2084 TTL 74-series IC LIST internal circuitry for sr flip flop T flip flop IC LS248 4-bit bcd subtractor
Contextual Info: SG 6 0R 4 Schottky TTL • O v e r 180 LS Devices • ALS • FAST • TTL C o m p a tib le M acrocell A rra y s • RAMs • PR O M s 006844 /y err This Material Copyrighted By Its Respective Manufacturer General Inform ation TTL in Perspective proved speed — p o w e r product co m p ared to LS as a

LS112A

Abstract: SN54LS112 SN54LS112A SN54S112 SN74 SN74LS112A SN74S112A
Contextual Info: SN5 4 L S 112A, SN5 4 S 112, SN7 4 L S 112A, SN7 4 S 112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP FLOPS WITH PRESET AND CLEAR D 2 6 6 1 . A P R IL 1 9 8 2 - R E V IS E D M A R C H 1 9 8 8 Fully Buffered to Offer Maximum Isolation from External Disturbance S N 5 4 L S 1 1 2 A . S N 5 4 S 1 1 2 . . . J OR W P A C K A G E

LS112A

Abstract: ALS112A
Contextual Info: DOT A VG Semiconductors 112 Technical Data Dual JK Negative Edge-Triggered Flip-Flops LS112A LS112A N Suffix Plastic DIP AVG -003 Case This device contains two individual J. K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock pulse goes

Contextual Info: AVG Semiconductors_ DDiT 112 Technical Data Dual JK Negative Edge-Triggered Flip-Flops LS112A LS112A N Suffix Plastic DIP AVG-003 Case This device contains two individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock pulse goes

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) JM38510/07102BEA ACTIVE CDIP

74aLS808

Abstract: 74ALS677 74ALS468 SN74AS877 SN74LS630 SM54A NCE 7190 74ls631 SN74LS693 TTL Data Book for Design Engineers
Contextual Info: ADVANCED LOW-POWER SCHOTTKY AND ADVANCED SCHOTTKY CIRCUITS FUNCTION DEVICE AS1032 ALS1034 AS1034 Quad 2-Input OR Buffers/ Drivers A VAILABILITY NOW NOW NOW Hex Drivers NOW ALS1035 Hex Buffers with D-C Outputs NOW AS1036 Quad 2-Input NOR Line Driver NOW ALS1240

SN7401

Abstract: National Semiconductor 4045 transistor bf 175 74ALS569 74AS1008 SN7449 SN74ALS244A SN54ALS1000A SN74ALS519 SN54ALS27
Contextual Info: GENERAL INFORMATION ORDERING INSTRUCTIONS AND MECHANICAL DATA FUNCTIONAL INDEX/SELECTION GUIDE PRODUCT GUIDE ADVANCED LOW-POWER SCHOTTKY AND ADVANCED SCHOTTKY CIRCUITS PROGRAMMABLE LOGIC ARRAYS BETA PRODUCTS EXPLANATION OF NEW LOGIC SYMBOLS CONNECTOR AND KEYBOARD PRODUCTS

LM 4017 decade counter driver

Abstract: 74HC7244A 74HCT7007A 74HC11A 74HC85A 74HC147 decimal to binary encoder cmos 4008 74HC21A 74HC07A 74HC7244
Contextual Info: 2.H IG H SPEED CMOS SELECTION GUIDE NÄ N D NOR A ND OR IN V E R T E R ,B U F FE R 74HC00A 74HCT00A 74HC03A 74HC10A 74HC20A 74HC30 71HC132A 74HC133A GATE 74HC02A 74HCT02A 74HC27A 74HC4002A 74HC4078 74HC08A 74HCT08A 74HC09A 74HC11A 74HC21A 74HC32A 74HCT32A 74HC4072

Contextual Info: TYPES LS112A, SN54S112, LS112A, SN74S112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR REVISED DECEMBER 1983 Fully Buffered to Offer Maximum Isolation from External Disturbance S N 5 4 L S 11 2 A , S N 5 4 S 1 1 2 . . . J OR W PACKAG E