LOGIC DIAGRAM CIRCUIT Search Results

74S00

Abstract: ScansUX1001
Contextual Info: FAIRCHILD SUPER HIGH SPEED TTL/SSI • 9S00/54S00, 74S00 QUAD 2-INPUT NAND GATE LOGIC AND CONNECTION DIAGRAM SCHEMATIC DIAGRAM DIP TOP VIEW (EACH GATE) V c c _ _ ' i£J L£>i üjyjLIJLilLÜLàJUJ GND Positive logic: Y = AB RECOMMENDED OPERATING CONDITIONS

isp1024

Abstract: 0127A-24-80-isp 102480LJ PLSI 1024-60LJ 5962-9476101mx 5962-9476101 1024-60LJ
Contextual Info: ispLSI and pLSI 1024 ® High-Density Programmable Logic Functional Block Diagram unctional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — High-Speed Global Interconnect — 4000 PLD Gates — 48 I/O Pins, Six Dedicated Inputs — 144 Registers — Wide Input Gating for Fast Counters, State

LED3-3

Abstract: LED30 SL70D0948 PWM generator LED34
Contextual Info: SLS System Logic Semiconductor SL70D0948 48 OUTPUT LED DRIVER / 9 BIT PWM CONTROLLER SL70D0948 System Logic Semiconductor SLS System Logic Semiconductor CONTENTS INTRODUCTION BLOCK DIAGRAM PIN ASSIGNMENT PIN DESCRIPTION FUNCTION DESCRIPTION SPECIFICAIONS REFERENCE APPLICATIONS

PIC12C508 tmr0

Abstract: 12C508 4014 Led here we go again movlw application note PIC12C508 12c508 timer
Contextual Info: Discrete Logic Replacement Logic Switch with Clock Generator Author: Marc Lemay Quebec, Canada email: MLemay@CollegeShawinigan.qc.ca Block Diagram: PIC12C508-04/P Switch Sw1 GP3 APPLICATION OPERATION: The first application of my Logic Switch is to help prototyping of a digital circuit. There are two main functions:

16L8A

Abstract: 16R8 214Z Fairchild logic/connection diagrams ttl 16L8 16R4 16R6 16R8A 16R8ADC
Contextual Info: . / / 16L8A, 16R8A, 16R6A, 16R4A Programmable Logic Array FAIRCHILD A Schtumberger Company September 1986 PRELIMINARY INFORMATION * i Memory & High Speed Logic Description Connection Diagram The FASTPLA 16L8A Series of high-performance bipolar programmable logic arrays provide 25 ns maximum

Contextual Info: ispLSI 5256VE In-System Programmable 3.3V SuperWIDE High Density PLD Functional Block Diagram Input Bus Generic Logic Block Boundary Scan Interface Input Bus Generic Logic Block Input Bus Input Bus Input Bus Generic Logic Block Generic Logic Block • Second Generation SuperWIDE HIGH DENSITY

5256VA

Abstract: 5384VA 5512VA 208-Pin PQFP b09 n03
Contextual Info: ispLSI 5256VA In-System Programmable 3.3V SuperWIDE High Density PLD Functional Block Diagram Input Bus Generic Logic Block Generic Logic Block Boundary Scan Interface Input Bus Generic Logic Block Input Bus Input Bus Input Bus Generic Logic Block • SuperWIDE HIGH DENSITY IN-SYSTEM

GLB3

Abstract: 0.4mm pitch BGA routing
Contextual Info: ispLSI 5256VE In-System Programmable 3.3V SuperWIDE High Density PLD Functional Block Diagram Input Bus Generic Logic Block Boundary Scan Interface Input Bus Generic Logic Block Input Bus Input Bus Input Bus Generic Logic Block Generic Logic Block • Second Generation SuperWIDE HIGH DENSITY

F10N12L

Abstract: F10N15L 10N15L F10N12 RFP10N15L F10N15 RFP10N12L 10n15 RFM10N12L RFM10N15L
Contextual Info: Logic-Level Power MOSFETs_ RFM10N12L, RFM10N15L, RFP10N12L, RFP10N15L File N u m be r 1559 Power Logic Level MOSFETs N-Channel Logic Level Power Field-Effect Transistors L2 FET TERMINAL DIAGRAM 10 A, 120 V — 150 V rDsioni: 0.3 f)

5000VA

Contextual Info: ispLSI 5256VE In-System Programmable 3.3V SuperWIDE High Density PLD Functional Block Diagram Input Bus Generic Logic Block Boundary Scan Interface Input Bus Generic Logic Block Input Bus Input Bus Input Bus Generic Logic Block Generic Logic Block • Second Generation SuperWIDE HIGH DENSITY

dhvqfn14

Abstract: 74AHCT08D NXP 74AHC08 74AHC08BQ 74AHC08D 74AHC08PW 74AHCT08 74AHCT08D 74AHCT08PW JESD22-A114E
Contextual Info: 74AHC08; 74AHCT08 NXP Semiconductors Quad 2-input AND gate 4. Functional diagram 1 & 3 & 6 2 1 1A 2 1B 4 2A 5 2B 9 3A 10 3B 12 4A 13 4B 1Y 3 4 2Y 6 5 3Y 8 9 A Y & 8 B 10 4Y mna221 11 12 mna222 & 11 13 mna223 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram one gate

5000VA

Abstract: 0.4mm pitch BGA
Contextual Info: ispLSI 5256VE In-System Programmable 3.3V SuperWIDE High Density PLD Functional Block Diagram Input Bus Generic Logic Block Boundary Scan Interface Input Bus Generic Logic Block Input Bus Input Bus Input Bus Generic Logic Block Generic Logic Block • Second Generation SuperWIDE HIGH DENSITY

10198

Abstract: 93L22 K9F1G08U0C-PCB0 93L22DMQB 93L22FMQB C1995 J16A W16A
Contextual Info: 93L22 Quad 2-Input Multiplexer General Description Features The 93L22 quad 2-input digital multiplexers consist of four multiplexing circuits with common select and enable logic each circuit contains two inputs and one output Y Connection Diagram Logic Symbol

9N40

Abstract: ScansUX1000 5440
Contextual Info: FAIRCHILD TT L/SSI . 9N40/5440, 7440 DUAL 4-INPUT NAND BUFFER LOGIC AND CONNECTION DIAGRAM DIP TOP VIEW SCHEMATIC DIAGRAM (EACH GATE) FLATPAK (TOP VIEW) R Pirafn uiflFlR BJ T ?-1 NC Positive logic: Vr r NC Y = ABCD C o m p o n e n t values show n are ty p ic a l.

7402 quad 2- input nor gate

Abstract: 7402 quad 2 input not 7402 TTL 7402 logic diagram 7402 NOR gate 7402 ttl gate 9N02 9N02 7402 TTL 7402 9N02/7402
Contextual Info: FAIRCHILD TT L/SSI • 9N02/5402, 7402 QUAD 2-INPUT NOR GATE SCHEMATIC DIAGRAM EACH GATE LOGIC AND CONNECTION DIAGRAM DIP (TOP VIEW) FLATPAK (TOP VIEW) T5TS1 ra r?l Positive logic: Y = A+B C o m p o n e n t values show n are ty p ic a l. RECOMMENDED OPERATING CONDITIONS

Contextual Info: Lattice Semiconductor G000717 saatTm 4 • GAL6001 High Performance E2CMOS Generic Array Logic Corporation FUNCTIONAL BLOCK DIAGRAM FEATURES • ELECTRICALLY ERASABLE CELL TECHNOLOGY — Instantly Reconflgurable Logic — Instantly Reprogrammable Cells

Contextual Info: 16L8A, 16R8A, 16R6A, 16R4A Programmable Logic Array FA IR C H ILD A Schlum berger Company September 1986 PRELIMINARY INFORMATION WL Memory & High Speed Logic Description Connection Diagram The FASTPLA 16L8A Series of high-performance bipolar programmable logic arrays provide 25 ns maximum

Contextual Info: ispLSI 2064V High-Density Programmable Logic Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC • • • ispEXPERT – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results

CIRCUIT SCHEMATIC ECU

Contextual Info: 10118B,F LOGIC DIAGRAM CIRCUIT SCHEMATIC B,F PACKAGE [> 11 u 12 0 — 1 hO 1 [> V e c i - ’ •VCC2 - ,6 ' VEE ■ Positive logic: high level = '1' FEATURES • Fast propagation delay lor 2 logic levels = 2.3 ns TYP • Low power dissipation = 100mW/package TYP no load

Contextual Info: 10121B.F LOGIC DIAGRAM CIRCUIT SCHEM ATIC B,F PACK AG E VCC1 ' 1. V c c 2 = 16' V EE = f Positive logic: high level = " l " FEATURES •Fast propagation delay for 2 logic levels = 2.3 ns TYP •Low power dissipation - 100 mW/package TYP no load •High fanout capability — can drive two

Contextual Info: 40 CONNECTION DIAGRAM PIN O U T A - o'1 9340 4-BIT ARITHMETIC LOGIC UNIT With Carry Lookahead DESCRIPTION — The ’40 is a high speed arithmetic logic unit with full onchip carry lookahead circuitry. It can perform the arithmetic operations add

Contextual Info: 54ACT11534,74ACT11534 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SCASQ38A- D2957, JULY 1987 - REVISED APRIL 1883_ logic diagram positive logic logic symbolt 24 55 rs 13 >C 1 CLK n 1D r i 2 2D _ _ 1Q 1Q 1D •V 20 3 4

AL6001

Abstract: al 6001 20 pin IC AL 6001 ic al6001 GAL6001-35P IC AL 6001 GAL6001-30P GAL6001-30J
Contextual Info: Lattice FEATURES GAL6001 High Performance E2CMOSFPLA Generic Array Logic FUNCTIONAL BLOCK DIAGRAM ELECTRICALLY ERASABLE CELL TECHNOLOGY — Instantly Reconflgurable Logic — Instantly Reprogrammable Cells — Guaranteed 100% Yields •HIGH PERFORMANCE E’CMOS TECHNOLOGY

Contextual Info: L 16L8B, 16R8B, 1 16R6B, 16R4B Programmable Logic Array F A IR C H IL D A Schlumberger Company September 1986 PRELIMINARY INFORMATION Memory & High Speed Logic Description Connection Diagram The FASTPLA 16L8B Series of high-performance bipolar programmable logic arrays provide 15 ns maximum