LOGIC DIAGRAM CIRCUIT Search Results

isp1024

Abstract: 0127A-24-80-isp 102480LJ PLSI 1024-60LJ 5962-9476101mx 5962-9476101 1024-60LJ
Contextual Info: ispLSI and pLSI 1024 ® High-Density Programmable Logic Functional Block Diagram unctional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — High-Speed Global Interconnect — 4000 PLD Gates — 48 I/O Pins, Six Dedicated Inputs — 144 Registers — Wide Input Gating for Fast Counters, State

F10N12L

Abstract: F10N15L 10N15L F10N12 RFP10N15L F10N15 RFP10N12L 10n15 RFM10N12L RFM10N15L
Contextual Info: Logic-Level Power MOSFETs_ RFM10N12L, RFM10N15L, RFP10N12L, RFP10N15L File N u m be r 1559 Power Logic Level MOSFETs N-Channel Logic Level Power Field-Effect Transistors L2 FET TERMINAL DIAGRAM 10 A, 120 V — 150 V rDsioni: 0.3 f)

dhvqfn14

Abstract: 74AHCT08D NXP 74AHC08 74AHC08BQ 74AHC08D 74AHC08PW 74AHCT08 74AHCT08D 74AHCT08PW JESD22-A114E
Contextual Info: 74AHC08; 74AHCT08 NXP Semiconductors Quad 2-input AND gate 4. Functional diagram 1 & 3 & 6 2 1 1A 2 1B 4 2A 5 2B 9 3A 10 3B 12 4A 13 4B 1Y 3 4 2Y 6 5 3Y 8 9 A Y & 8 B 10 4Y mna221 11 12 mna222 & 11 13 mna223 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram one gate

5000VA

Abstract: 0.4mm pitch BGA
Contextual Info: ispLSI 5256VE In-System Programmable 3.3V SuperWIDE High Density PLD Functional Block Diagram Input Bus Generic Logic Block Boundary Scan Interface Input Bus Generic Logic Block Input Bus Input Bus Input Bus Generic Logic Block Generic Logic Block • Second Generation SuperWIDE HIGH DENSITY

Contextual Info: Lattice Semiconductor G000717 saatTm 4 • GAL6001 High Performance E2CMOS Generic Array Logic Corporation FUNCTIONAL BLOCK DIAGRAM FEATURES • ELECTRICALLY ERASABLE CELL TECHNOLOGY — Instantly Reconflgurable Logic — Instantly Reprogrammable Cells

Contextual Info: 16L8A, 16R8A, 16R6A, 16R4A Programmable Logic Array FA IR C H ILD A Schlum berger Company September 1986 PRELIMINARY INFORMATION WL Memory & High Speed Logic Description Connection Diagram The FASTPLA 16L8A Series of high-performance bipolar programmable logic arrays provide 25 ns maximum

Contextual Info: ispLSI 2064V High-Density Programmable Logic Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC • • • ispEXPERT – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results

CIRCUIT SCHEMATIC ECU

Contextual Info: 10118B,F LOGIC DIAGRAM CIRCUIT SCHEMATIC B,F PACKAGE [> 11 u 12 0 — 1 hO 1 [> V e c i - ’ •VCC2 - ,6 ' VEE ■ Positive logic: high level = '1' FEATURES • Fast propagation delay lor 2 logic levels = 2.3 ns TYP • Low power dissipation = 100mW/package TYP no load

Contextual Info: 10121B.F LOGIC DIAGRAM CIRCUIT SCHEM ATIC B,F PACK AG E VCC1 ' 1. V c c 2 = 16' V EE = f Positive logic: high level = " l " FEATURES •Fast propagation delay for 2 logic levels = 2.3 ns TYP •Low power dissipation - 100 mW/package TYP no load •High fanout capability — can drive two

Contextual Info: 40 CONNECTION DIAGRAM PIN O U T A - o'1 9340 4-BIT ARITHMETIC LOGIC UNIT With Carry Lookahead DESCRIPTION — The ’40 is a high speed arithmetic logic unit with full onchip carry lookahead circuitry. It can perform the arithmetic operations add

Contextual Info: 54ACT11534,74ACT11534 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SCASQ38A- D2957, JULY 1987 - REVISED APRIL 1883_ logic diagram positive logic logic symbolt 24 55 rs 13 >C 1 CLK n 1D r i 2 2D _ _ 1Q 1Q 1D •V 20 3 4

Contextual Info: L 16L8B, 16R8B, 1 16R6B, 16R4B Programmable Logic Array F A IR C H IL D A Schlumberger Company September 1986 PRELIMINARY INFORMATION Memory & High Speed Logic Description Connection Diagram The FASTPLA 16L8B Series of high-performance bipolar programmable logic arrays provide 15 ns maximum

D3609

Abstract: 74ACT11544
Contextual Info: 74ACT11544 OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCAS133 - D3609, JULY 1990 - REVISED APRIL 1993_ logic diagram positive logic logic symbolt B1 To Seven O the r T ra n sceive rs t This symbol is in accordance with ANSI/I EEE Std 91-1984

Contextual Info: Specifications ispLSI and pLS11024 Lattice ispLSr and pLSI 1024 ;Semiconductor I Corporation High-Density Programmable Logic Features Functional Block Diagram HIGH-DENSITY PROGRAMMABLE LOGIC — — — — — High-Speed Global Interconnect 4000 PLD Gates

10190F

Abstract: 10181F 10181
Contextual Info: 10181F DESCRIPTION BLOCK DIAGRAM The 10181 is an extremely versatile high speed arithmetic logic unit capable of performing 16 logic operations and 16 arithmetic func­ tions on two four-bit words. Using advanced circuit design techniques and double layer metalization the 10181 represents the

Contextual Info: 10117-B.F LOGIC DIAGRAM CIRCUIT SCHEMATIC B,F PACKAGE L . 6 s - 6 0 — i C J r L 10 o — n c ^ J q 1 2 0 - r - v 1 3 0 - J j - VCC1 = V C C 2 * 16' V EE Positive logic: high level = “ i 8 FEATURES •Fast propagation delay for two logic

EP310 programmable

Abstract: Altera ep310
Contextual Info: ^ 8 MACROCELL EPLD FEATURES EP310 EP310 GENERAL DIAGRAM Programmable replacement for conventional fixed logic. EPROM technology allows reprogrammability, ensures high programming yield and ease of use. Second generation programmable logic architecture allows up to 18 inputs and

Contextual Info: 10114F LOGIC DIAGRAM CIRCUIT SCHEMATIC F PACKAGE V CC1 — O -0 3 V CC2 -O I f VCC1 * '• VCC2 - 16' VEE Positive logic: high level = " 1 ” >• FEATURES ■Guaranteed common mode noise rejection of 1 volt * Fast propagation delay = 2.0na TYP differential input

Contextual Info: Lattice ispLSr 1048 in-system programmable Large Scale Integration High-Density Programmable Logic Features Functional Block Diagram IN-SYSTEM PROGRAMMABLE HIGH-DENSITY LOGIC — Member of Lattice’s ispLSI Family — Fully Compatible with Lattice's pLSI Family

yd4a

Contextual Info: ispLSI and pLSI 2128V ® 3.3V High-Density Programmable Logic Features Functional Block Diagram* • HIGH DENSITY PROGRAMMABLE LOGIC • HIGH PERFORMANCE E2CMOS® TECHNOLOGY Electrically Erasable and Reprogrammable Non-Volatile 100% Tested at Time of Manufacture

Contextual Info: PRELIMINARY 54LVTH245A 3.3V ABT Octal Bus Transceiver with 3-State Output Memory Logic Diagram Positive Logic FEATURES: DESCRIPTION: • 3.3V ABT octal bus transceiver with 3-state outputs • RAD-PAK radiation hardened against natural space radiation

B272

Abstract: z 0607
Contextual Info: ispLSI 3192 Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic

9852

Abstract: schematic diagram vga schematic diagram cga to vga
Contextual Info: PLE40 \ LOGIC APS SCHEMATIC CAPTURE SOFTWARE PLE40 CONTENTS GENERAL DESCRIPTION SOFTWARE Digital logic designs are often o rigin ally con­ ceived in the form of a logic or schematic diagram. The engineer wishing to take advantage of the many benefits of the new high density program ­

Contextual Info: Lattice' | Semiconductor I Corporation ispLSI9 and pLSt 1048C High-Density Programmable Logic Features Functional Block Diagram HIGH-DENSITY PROGRAMMABLE LOGIC — 8000 PLD Gates — 96 I/O Pins, 12 Dedicated Inputs, 2 Global Output Enables — 288 Registers