LOAD CELL PSOC Search Results

Contextual Info: CY14E256LA 256-Kbit 32 K x 8 nvSRAM 256-Kbit (32 K × 8) nvSRAM Features Functional Description • 25 ns and 45 ns access times ■ Internally organized as 32 K × 8 (CY14E256LA) ■ Hands-off automatic STORE on power-down with only a small capacitor ■

IMO PLC k7

Abstract: MP-55 cy8c24794-24ltxi CY320 CY325 cy8c244 336-7463 CY8C29X CY-320
Contextual Info: CY8C24094, CY8C24794 CY8C24894, CY8C24994 PSoC Programmable System-on-Chip PSoC® Programmable System-on-Chip 1. Features XRES pin to support in-system serial programming ISSP and external reset control in CY8C24894 • Powerful Harvard-architecture processor

Contextual Info: CY14B108L CY14B108N 8-Mbit 1024 K x 8/512 K × 16 nvSRAM 8-Mbit (1024 K × 8/512 K × 16) nvSRAM Features • Packages ❐ 44-/54-pin thin small outline package (TSOP) Type II ❐ 48-ball fine-pitch ball grid array (FBGA) Pb-free and restriction of hazardous substances (RoHS)

PSOC LCD 1289

Abstract: dtmf tranmitter 072ps
Contextual Info: CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 PSoC Programmable System-on-Chip Features • ■ ■ ■ ■ ■ Pull-up, pull-down, high Z, strong, or open-drain drive modes

Contextual Info: CY7C1370D, CY7C1372D 18-Mbit 512 K x 36/1 M × 18 Pipelined SRAM with NoBL Architecture 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™

CY7C15632KV18

Abstract: 3M Touch Systems
Contextual Info: CY7C15632KV18 72-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions

CY8C29466

Contextual Info: CY8C29466, CY8C29666 Automotive – Extended Temperature PSoC Programmable System-on-Chip Features • AEC qualified ■ Powerful Harvard-Architecture processor ❐ M8C processor speeds up to 12 MHz ❐ Two 8 x 8 multiply, 32-bit accumulate ❐ Low power at high speed

CY7C1370DV25-167BZI

Contextual Info: CY7C1370DV25 CY7C1372DV25 18-Mbit 512 K x 36/1 M × 18 Pipelined SRAM with NoBL Architecture 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™

Contextual Info: CY7C25442KV18 72-Mbit QDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency with ODT 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features • Separate independent read and write data ports ❐ Supports concurrent transactions

Contextual Info: CY7C1441AV33 36-Mbit 1 M x 36 Flow-Through SRAM 36-Mbit (1 M × 36) Flow-Through SRAM Features Functional Description • Supports 133-MHz bus operations ■ 1 M × 36 common I/O ■ 3.3 V core power supply ■ 2.5 V or 3.3 V I/O power supply ■ Fast clock-to-output times

CY8C3665

Abstract: 8051 8bit microcontroller cy8c3665lti-006
Contextual Info: PSoC 3: CY8C36 Family Data Sheet ® Programmable System-on-Chip PSoC General Description With its unique array of configurable blocks, PSoC® 3 is a true system level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C36 family offers a modern method of signal acquisition, signal

bzx 850

Abstract: bzx 850 30
Contextual Info: CY7C1412AV18 CY7C1414AV18 36 Mbit QDR II SRAM Two Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■ 2-word burst on all accesses

Contextual Info: CY7C1381D CY7C1383D, CY7C1383F 18-Mbit 512 K x 36/1 M × 18 Flow-Through SRAM 18-Mbit (512 K × 36/1 M × 18) Flow Through SRAM Features Functional Description • Supports 133 MHz bus operations ■ 512 K × 36 and 1 M × 18 common I/O ■ 3.3 V core power supply (VDD)

1000 watt audio amplifier circuit diagram

Contextual Info: PSoC 3: CY8C38 Family Data Sheet ® Programmable System-on-Chip PSoC General Description With its unique array of configurable blocks, PSoC® 3 is a true system level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C38 family offers a modern method of signal acquisition, signal

CANopen

Abstract: ua 741 opamp PAL Decoder 8051 Nand gate Crystal Oscillator 7144-1
Contextual Info: PSoC 3: CY8C38 Family Data Sheet ® Programmable System-on-Chip PSoC General Description With its unique array of configurable blocks, PSoC® 3 is a true system level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C38 family offers a modern method of signal acquisition, signal

Contextual Info: CY7C1518KV18 CY7C1520KV18 72-Mbit DDR II SRAM Two-Word Burst Architecture 72-Mbit DDR II SRAM Two-Word Burst Architecture Features Configurations • 72-Mbit density 4 M x 18, 2 M × 36 CY7C1518KV18 – 4 M × 18 ■ 333 MHz clock for high bandwidth CY7C1520KV18 – 2 M × 36

CY7C1318KV18

Abstract: CY7C1318KV18-250 CY7C1320KV18
Contextual Info: CY7C1316KV18, CY7C1916KV18 CY7C1318KV18, CY7C1320KV18 18-Mbit DDR II SRAM Two-Word Burst Architecture 18-Mbit DDR II SRAM Two-Word Burst Architecture Features Configurations • 18-Mbit density 2 M x 8, 2 M × 9, 1 M × 18, 512 K × 36 CY7C1316KV18 – 2 M × 8

CY7C25632

Abstract: 3M Touch Systems
Contextual Info: CY7C25632KV18 CY7C25652KV18 72-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency with ODT 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features • JTAG 1149.1 compatible test access port ■

Contextual Info: CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 72-Mbit QDR II SRAM Two-Word Burst Architecture 72-Mbit QDR® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1525KV18 – 8 M x 9

AN5062

Contextual Info: CY7C1318BV18, CY7C1320BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces

CY7C2263KV18

Abstract: 3M Touch Systems
Contextual Info: CY7C2263KV18, CY7C2265KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency with ODT 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations • Separate independent read and write data ports

CY7C1515KV18-300BZXI

Contextual Info: CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 72-Mbit QDR II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1526KV18 – 8 M x 9 ■ 333 MHz clock for high bandwidth

CY7C1512KV18-250BZXI

Contextual Info: CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 72-Mbit QDR II SRAM 2-Word Burst Architecture 72-Mbit QDR® II SRAM 2-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions

Contextual Info: CY7C1411KV18, CY7C1426KV18 CY7C1413KV18, CY7C1415KV18 36-Mbit QDR II SRAM 4-Word Burst Architecture 36-Mbit QDR® II SRAM 4-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions