LINK MANAGEMENT PROTOCOL Search Results

Uart applications

Abstract: SiW1602 SiW1502 32KHZ long wave RADIO Odyssey bluetooth wireless encrypt Hitachi DSA00103
Contextual Info: SiW1602 Data Sheet Preliminary Information February 5, 2001 SiW1602 Link Controller IC 1. INTRODUCTION The Odyssey SiW1602 Link Controller IC is part of Silicon Wave's solutions for Bluetooth™ wireless communications. The SiW1602 provides the Bluetooth link management and control functions in a digital

mobile phone microprocessor IC

Abstract: IC link SiW1601 SiW1502 all ic data all ic datasheet 32KHZ 32KHZCLK 32 MHZ OSCILLATOR wireless encrypt
Contextual Info: SiW1601 Data Sheet Preliminary Information October 11, 2000 SiW1601 Link Controller IC 1. INTRODUCTION The SiW1601 Link Controller IC is part of Silicon Wave's Odyssey solutions for Bluetooth™ wireless communications. The SiW1601 IC provides the Bluetooth link management and control functions in a

101-Key

Abstract: 8042 Keyboard Controller 8042 PS2 ps2 CIRCUIT power diagram PS2 keyboard PROTOCOL 32-PIN AT-101 MAX232 PC9800 UR6HCPS2-SP40
Contextual Info: PS2Adapt UR6HCPS2-SP40 Converts PS/2 Data to Serial or SPI HID & SYSTEM MANAGEMENT PRODUCTS, SYSTEM MANAGEMENT FAMILY DESCRIPTION The PS2Adapt™ UR6HCPS2-SP40 is an extremely low-power protocol interpreter that can link an AT / PS/2-compatible Human Input

Infrared Data Access

Contextual Info: Vishay Telefunken Appendix List of Terms and Abbreviations : IrDA Infrared Data Association IrLAP IrDA Link Access Protocol IrLMP Link Management Protocol IrPHY IrDA Physical Layer Ir TRAN-P

Signia Technologies

Abstract: SGN5010 SGN3100 PHY LQFP80 cyclic redundancy check
Contextual Info: Ulysses SGN3100 Bluetooth™ Baseband IC PRELIMINARY SPECIFICATION Product Description: Key Features: The Ulysses™ SGN3100 provides Bluetooth™ Link Control and Link Management functions that support up to 8 data/3 voice channels compliant with the Bluetooth™ Specification 1.1. The SGN3100 contains a

TSB11C01

Abstract: X3T13 tailgate Silicon Systems 6914 TSB11LV01 TSB21LV03 atapi 39C1010 1394 tailgate
Contextual Info: SSI 39C1010 1394-ATA/ATAPI Tailgate Link Controller Target Specification January 1997 SBP-2 protocol • Implement SBP-2 management and command fetch, decode and execute • Implement SBP-2 and tailgate registers • Supports two logical units • Configuration ROM

SMBus

Abstract: LTC1694
Contextual Info: advertisement SMBus Accelerator Improves Data Integrity – Design Note 193 David Bell and Mark Gurries Introduction The System Management Bus SMBus is gaining popularity in portable computers as a communication link between smart batteries, the battery charger and the

SBI Temperature Sensor Interface SB-TSI

Abstract: SB-TSI AMD 40821 45937 SBI Temperature Sensor Interface SB-TSI Specification, #40821 SBI Temperature Sensor Interface SB-TSI Specification, AMD Family 12h amd 10h family F-3X amd apml
Contextual Info: 41918 Rev 1.02 - August 25, 2009 APML Specification Cover page Advanced Platform Management Link APML Specification Advanced Micro Devices 1 41918 Rev 1.02 - August 25, 2009 APML Specification 2006-2009 Advanced Micro Devices, Inc. All rights reserved.The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes

OIF-CEI-020

Abstract: CRC-32 LFSR vhdl code for crc16 using lfsr link management protocol CRC-16 CRC-32 PD10 0xC704DD7B vhdl code 8 bit LFSR S/BIP/SCB345100/B/30/ProtoMat D104
Contextual Info: SerialLite II Protocol Reference Manual 101 Innovation Drive San Jose, CA 95134 408 544-7000 www.altera.com Document Version: Document Date: 1.0 October 2005 Copyright 2005 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

t801 transformer

Abstract: t592
Contextual Info: November 1999 DP83846A DsPHYTER — Single 10/100 Ethernet Transceiver General Description Features The DP83846A is a full feature single Physical Layer device with integrated PMD sublayers to support both 10BASE-T and 100BASE-TX Ethernet protocols over Category 3 10 Mb/s or Category 5 unshielded twisted pair

82551ER

Abstract: 82551IT 82551QM 82559ER intel material declaration 82559ER GD82551ER T57 transformer datasheet
Contextual Info: 82551ER Fast Ethernet PCI Controller Networking Silicon - 82551ER Datasheet Product Features • ■ ■ ■ ■ ■ ■ Enhanced IP Protocol Support — TCP, UDP, IPv4 checksum offload — Received checksum verification Quality of Service QoS — Multiple priority transmit queues

nvidia application notes

Abstract: 5VLX330-1
Contextual Info:  Compliant with PCI Express Base Specification 1.1  Implements Transaction, Data CPXP-EPx8 PCI Express Endpoint Controller Core with SoC Bridge Extensions for AMBA AXI Link, and Physical protocol layers in hardware  Supports x8 link width  Offers a data rate of 2.5 Gbps

circuit diagram of PAM transmitter and receiver

Abstract: PAM-5 17-LEVEL 1000base high speed line driver GMII layout
Contextual Info: Preliminary - Content Subject to Change L80601 Ultra Low Power 10/100/1000 Mbits/s PHY Preliminary Datasheet The L80601 is a full-featured Physical Layer PHY transceiver with integrated Physical Media Dependent (PMD) sublayers to support 10BASE-T, 100BASE-TX, and 1000BASE-T Ethernet protocols.

Cyclic Redundancy Check simulation

Abstract: PCI AHB DMA nvidia register
Contextual Info: Compliant with PCI Express Base Specification 1.1 CPXP-EP PCI Express Endpoint Controller Core Implements a PCI Express endpoint controller that is compliant with PCI Express Base specification 1.1, including the Transaction, Data Link, and Physical protocol layers.

Contextual Info: Compliant with PCI Express Base Specification 1.1 CPXP-EP PCI Express Endpoint Controller Megafunction with SoC Bridge Extensions for AHB, AXI and Wishbone Implements a PCI Express endpoint controller that is compliant with PCI Express Base specification 1.1, including the Transaction, Data Link, and Physical protocol layers. It

Contextual Info: Compliant with PCI Express Base Specification 1.1 CPXP-EPx8 PCI Express Endpoint Controller Core with SoC Bridge Extensions for AMBA AXI Implements a PCI Express endpoint controller that is compliant with PCI Express Base specification 1.1, including the Transaction, Data Link, and Physical protocol layers. It

LU82551IT

Abstract: 82551IT FLA2 LU82551IT datasheet Three-Five 82551ER 82551QM 82559ER
Contextual Info: 82551IT Fast Ethernet PCI Controller Networking Silicon - 82551IT Datasheet Product Features • ■ ■ ■ ■ ■ ■ Enhanced IP Protocol Support — TCP, UDP, IPv4 checksum offload — Received checksum verification Quality of Service QoS — Multiple priority transmit queues

gvrp

Abstract: IC 4094 PM3370
Contextual Info: Preliminary Information EXACTTM ETHERNET SWITCHING MICROCODE STANDARDS SUPPORT EXACT MICROCODE ARCHITECTURE • Standards supported: IEEE 802.3 and Ethernet protocols IEEE 802.3z Gigabit Ethernet IEEE 802.3ab Copper Gigabit Ethernet IEEE 802.3u 100Base-T C o m m u n ic a t io n s

GD82551IT

Abstract: LU82551IT 82551IT LU82551IT datasheet 82551ER 82551QM 82559ER L77C
Contextual Info: 82551IT Fast Ethernet PCI Controller Networking Silicon - 82551IT Datasheet Product Features        Enhanced IP Protocol Support — TCP, UDP, IPv4 checksum offload — Received checksum verification Quality of Service QoS — Multiple priority transmit queues

Contextual Info:  Compliant with PCI Express Base Specification 1.1  Implements Transaction, Data CPXP-EPx8 PCI Express Endpoint Controller Megafunction with SoC Bridge Extensions for AMBA AXI Link, and Physical protocol layers in hardware  Supports x8 link width

"network interface cards"

Contextual Info: DP83846A DsPHYTER — Single 10/100 Ethernet Transceiver General Description Features The DP83846A is a full feature single Physical Layer device with integrated PMD sublayers to support both 10BASE-T and 100BASE-TX Ethernet protocols over Category 3 10 Mb/s or Category 5 Unsheilded twisted pair

PCI AHB DMA

Abstract: tsmc 0.18 axi bridge
Contextual Info: Compliant with PCI Express Base Specification 1.1 CPXP-EP PCI Express Endpoint Controller Core with SoC Bridge Extensions for AHB, AXI and Wishbone Implements a PCI Express endpoint controller that is compliant with PCI Express Base specification 1.1, including the Transaction, Data Link, and Physical protocol layers. It

EM316OSSH

Abstract: MRV-FD-OSSH-120307 IC link
Contextual Info: Media Converters Repeaters and Optimizers Datasheet FD Optical Self-Healing Switch Features 1+1 hot stand-by path protection - Point-to-point - Ring Link switchover times of 10 ms or less Protocol independence 1260 nm through 1620 nm wavelength range Maximum insertion loss of 5 dB per link

JDSU Transponder

Abstract: Dispersion Compensation Module RELAY 1551 GR-63-CORE WRT-740 BUDGET adm* maj
Contextual Info: COMMUNICATIONS MODULES & SUBSYSTEMS Long Reach, Client-Side SFP, Multi-Rate, Multi-Protocol, CWDM, 3R Transponder WaveReady Transponder 740 LR CWDM Key Features • Client-side SFP modules support either single-mode SMF or multi-mode fiber (MMF) • Automatic bit rate detection and reporting