K33 SMC Search Results

j35 SMD Marking Code

Abstract: 152J50J31 EVOX RIFA SMC CAPACITORS k33 smc 104j100 223j100 154J100
Contextual Info: SMC RoHS • Metallized polyphenylene sulphide PPS SMD • According to IEC 60384-20 typical applications Timing, filtering. Memory capacitor. High stability and accuracy. High temperature use. Compliant Construction H 0.5 Polyphenylene sulphide (PPS) film

j35 SMD Marking Code

Abstract: smc10.2
Contextual Info: SMC • Metallized polyphenylene sulphide PPS SMD • According to IEC 60384-20 TYPICAL APPLICATIONS CONSTRUCTION Timing, filtering. Memory capacitor. High stability and accuracy. High temperature use. H 0.5 Polyphenylene sulphide (PPS) film capacitor for surface mounting.

Contextual Info: General Purpose, High Stability and AC Line EMI Suppression SMC Series Encapsulated, Size 2220 – 6560, 50 – 400 VDC Overview Applications Polyphenylene sulphide PPS film capacitor for surface mounting. Encapsulation in self-extinguishing material meeting

Contextual Info: General Purpose, High Stability and AC Line EMI Suppression SMC Series Encapsulated, Size 2220 – 6560, 50 – 400 VDC Overview Applications Polyphenylene sulphide PPS film capacitor for surface mounting. Encapsulation in self-extinguishing material meeting

transistor c1850

Abstract: Samsung tv remote control circuit diagram k27 transistor KS5191 D560 transistor SMCS-51 S3C1850 C1850 transistor k58
Contextual Info: 2. S3C1850 S3C1850 DESCRIPTION S3C1850, a 4-bit single-chip CMOS microcontroller, consists of the reliable SMCS-51 CPU core with on-chip ROM and RAM. Eight input pins and 11 output pins provide the flexibility for various I/O requirements. Auto reset circuit generates reset pulse every certain period, and every halt mode termination time. The S3C1850

C1850

Abstract: Samsung tv remote control circuit diagram c1860 KS51899 SMCS-51 K9 samsung mov k25 c1860 remote SF 455 D transistor c1850
Contextual Info: 1. S3C1840 S3C1840 DESCRIPTION S3C1840, a 4-bit single-chip CMOS microcontroller, consists of the reliable SMCS-51 CPU core with on-chip ROM and RAM. Eight input pins and 11 output pins provide the flexibility for various I/O requirements. Auto reset circuit generates reset pulse every certain period, and every halt mode termination time. The S3C1840

Samsung tv remote control circuit diagram

Abstract: C185 transistor k54 KS5191 S3C1860 S3P1860 SMCS-51 transistor k52 S3C1840
Contextual Info: 3. S3C1860 S3C1860 DESCRIPTION S3C1860, a 4-bit single-chip CMOS microcontroller, consists of the reliable SMCS-51 CPU core with on-chip ROM and RAM. The S3C1860 is the microcontroller which has 1024 bytes mask-programmable ROM. The S3P1860 is the microcontroller which has 1024 bytes one-time-programmable EPROM. In the S3P1860, the

PR78A

Abstract: pr77a 2n2222 sot23 PR85A PR80C PR81A PL80B 22HP037 fairchild aa11 47H16M16BG
Contextual Info:  LatticeSC PCI Express x4 Evaluation Board User’s Guide September 2009 Revision: EB31_01.2  LatticeSC PCI Express x4 Evaluation Board User’s Guide Lattice Semiconductor Introduction This user’s guide describes the LatticeSC PCI Express x4 Evaluation Board featuring the LatticeSC

ROSENBERGER 32K243

Abstract: PL80B 32K243 fairchild aa30 pr77a Rosenberger HW-USBN-2A Schematic HW-USB PT60 PR76A
Contextual Info: LatticeSC PCI Express x8 Evaluation Board User’s Guide April 2007 Revision: EB19_01.3 LatticeSC PCI Express x8 Evaluation Board User’s Guide Lattice Semiconductor Introduction This user’s guide describes the LatticeSC PCI Express x8 Evaluation Board featuring the LatticeSC

CX950

Abstract: m155 version 02
Contextual Info: CX29600 OptiPHYTM - M155 STS-3 SONET/SDH Multiplexer CX29600 is a highly integrated, single-port chip that provides SONET/SDH processing and multiplexer/demultiplexer functions for a single STS-3/STM-1 data stream. All mappings are compliant with SONET/SDH standards including Bellcore GR-253, ANSI T1.105, and ITU G.707.

AH24A

Abstract: ATIC 164 D2 48 pin ATIC 164 D2 44 pin
Contextual Info: Virtex 2.5 V Field Program m able Gate Arrays £ X IU N X January 27, 1999 Version 1.2 Advance Product Specification Features • • • • • • Fast, high-density Field-Program m able Gate Arrays - Densities from 50k to 1M system gates - System perform ance up to 200 MHz

CX950

Abstract: 0X351
Contextual Info: CX29610 OptiPHYTM - M622 STS-12/4x STS-3 SONET/SDH Multiplexer Distinguishing Features • • • • • Processes combinations of STS-12, STS-3 payload framing/multiplexing for: – 1x STS-12/STM-4 – 4x STS-3/STM-1 Glueless connectivity to the CX29503/CX29513 and

marvel phy 88e1111 reference design

Abstract: Marvell 88E1111 layout guide SMD SOT23 transistor MARK Y2 88E1111 AN8077 smd k24 CW-P423-156.25MHZ C4161 BLM41PG600SN1L smd diode u1j
Contextual Info:  LatticeECP3 Serial Protocol Board – Revision D User’s Guide July 2010 Revision: EB44_01.3  Lattice Semiconductor LatticeECP3 Serial Protocol Board – Revision D User’s Guide Introduction The LatticeECP3 Serial Protocol Board referred to in this document as “SPB” allows designers to investigate and

C7L3

Abstract: c5m3 IC R2A3 FREE u4d1 C4A12 C4A15 sgpio cpld AM3301 b11 c18 101v 1p8 r7m10
Contextual Info: Host Bus Adapter Schematics for Intel R 8134x I/O Processors February 2007 Order Number: 315367-002US INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS

28f128j3d75

Abstract: 28F256P30 intel 28f256p30 28F128J3D L1F1 HDR_2X25 Amphenol af3 lm8365 intel strataflash j3d strataflash j3d
Contextual Info: External Storage Design Schematics for Intel R 8134x I/O Processors September 2006 Order Number: 315366-001US INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS

transistor pt36c

Abstract: pt36c PT35c transistor INTEL Core i5 760 PB7D pt35c k72 w5 OR3L165B8BM680-DB PB27A AL962
Contextual Info: Data Addendum March 2002 ORCA OR3LxxxB Series Field-Programmable Gate Arrays Introduction • ■ Features ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, 0.25 µm 5-level metal technology. 2.5 V internal supply voltage and 3.3 V I/O supply

432PIN

Contextual Info: Data Addendum December 1999 m icroelectronics group Lucent Technologies Bell Labs Innovations ORCA 0R3LxxxB Series Field-Programmable Gate Arrays Introduction This data addendum refers to the information found in the ORCA® Series 3C and 3T Field-Programmable

transistor pt36c

Abstract: pt35c PT35c transistor k72 v1 CHIP T 409 ES OR3L165B7BA352-DB or3l165b7bc432i-db GSrm PB27A OR3L165B8BM680-DB
Contextual Info: ORCA OR3LxxxB Series Device Datasheet June 2010 All Devices Discontinued! Product Change Notifications PCNs have been issued to discontinue all devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes.

APC-7 Calibration Kit

Abstract: BENDIX TEE CONNECTORS
Contextual Info: Agilent’s test accessories eliminate the weak links in your measurement system. • Guarantee accurate and repeatable results • Reduce cost of test Online Resources • Locate product and support information with simple navigation to technical overviews, manuals, news releases, education

6N0 953 235

Contextual Info: Preliminary Data Sheet microelectronics group Lucent Technologies Bell Labs Innovations ORCA OR3Cxx 5 V and OR3Txxx (3.3 V) Series Field-Programmable Gate Arrays Features • High-performance, cost-effective, 0.35 nm 4-level metal technology, with a migration plan to 0.25 urn

Contextual Info: Preliminary Data Sheet November 1997 m icroelectro nics group L u c m t T a d m o lo g lM Ball Labi In rn w tk m ORCA OR3Cxx 5 V and OR3Txxx (3.3 V) Series Field-Programmable Gate Arrays Features • High-performance, cost-effective, 0.35 |am 4-level metal technology, with a migration plan to 0.25 |am

T55M3

Abstract: CORE F5A OR3T80 ORCA
Contextual Info: Preliminary Data Sheet, Rev. 1 September 1998 ORCA Series 3 Field-Programmable Gate Arrays T Abundant hierarchical routing resources based on rout- Features T High-performance, cost-effective, 0.35 µm OR3C and T T T T T T T T T 0.3 µm (OR3T) 4-level metal technology, with a migration plan to 0.25 µm technology (4- or 5-input look-up

Contextual Info: Preliminary Data Sheet, Rev. 1 September 1998 m i c r o e l e c t r o n i c s group Lucent Technologies Bell Labs Innovations ORCA Series 3 Field-Programmable Gate Arrays Features • High-performance, cost-effective, 0.35 OR3C and 0.3 urn (OR3T) 4-level metal technology, with a migra­

Contextual Info: Data Sheet June 1999 microelectronics group Lucent Technologies Bell Labs Innovations ORCA Series 3C and 3T Field-Programmable Gate Arrays Features • High-performance, cost-effective, 0.35 pm OR3C and 0.3 pm (OR3T) 4-level metal technology, (4- or 5-input