K 3754 Search Results

Contextual Info: CY7C1354C CY7C1356C 9-Mbit 256 K x 36/512 K × 18 Pipelined SRAM with NoBL Architecture 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT ■

Contextual Info: CY7C1354CV25 CY7C1356CV25 9-Mbit 256 K x 36/512 K × 18 Pipelined SRAM with NoBL Architecture 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible with and functionally equivalent to ZBT™

Contextual Info: CY7C1354C CY7C1356C 9-Mbit 256 K x 36/512 K × 18 Pipelined SRAM with NoBL Architecture 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT ■

Contextual Info: CY7C1354C CY7C1356C 9-Mbit 256 K x 36/512 K × 18 Pipelined SRAM with NoBL Architecture 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM with NoBL™ Architecture Functional Description Features • Pin-compatible and functionally equivalent to ZBT ■

Contextual Info: CY7C1354CV25 CY7C1356CV25 9-Mbit 256 K x 36/512 K × 18 Pipelined SRAM with NoBL Architecture 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM with NoBL™ Architecture Functional Description Features • Pin-compatible with and functionally equivalent to ZBT™

Contextual Info: CY7C1360C, CY7C1362C 9-Mbit 256 K x 36/512 K × 18 Pipelined SRAM 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM Functional Description Features • Supports bus operation up to 200 MHz ■ Available speed grades: 200 MHz, and 166 MHz ■ Registered inputs and outputs for pipelined operation

Contextual Info: CY7C1360C, CY7C1362C 9-Mbit 256 K x 36/512 K × 18 Pipelined SRAM 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM Features Functional Description • Supports bus operation up to 200 MHz ■ Available speed grades: 200 MHz, and 166 MHz ■ Registered inputs and outputs for pipelined operation

2n7588

Abstract: P3139 BC233A sprague 40d GEX36/7 C4274 s1766 C12712 TC236 GP149
Contextual Info: SPRAGUE THE M A R K O F R E L I A B I L I T Y SEMICONDUCTOR REPLACEMENT MANUAL K -5 0 0 TABLE OF CONTENTS Guidelines for Replacing Semiconductors. 1 Specifications, Small-Signal and Power Transistors.

BIT 3713

Abstract: H8/520 H8/539 DP-64S H8/325 DTC 304-2 H8/532 32KB OTP CPU H8 534 hitachi 3048 flash security H8/322
Contextual Info: 11.03.1996 Interrupts internal, external Others - 16 k ROM +8k EEPROM 512 - - - 2 - - - - - - - - - - - - 8k EEPROM, security function, 3 V operation 8k 256 yes yes - 53 - 1 2 - - 2 - - - - - 17, 4 16 k, ROM-less 512 yes yes - 53 - 1 2 - - 2 - - - - - 17, 4

4 digits 12-segment led display

Contextual Info: O K I SEMICONDUCTOR GROUP 23E D • b75424D DODbSSS b O K I semiconductor_ MSC7110-XX/ MSC7112-xx_ 12-SEGMENT, 16-DIGIT/ 16-SEGMENT, 12-DIGIT GENERAL DESCRIPTION The MSC7110-xx and MSC7112-xx are general purpose display controllers for vacuum fluorescent

Contextual Info: 4bE D • b ? 2 4 2 4 0 OOllflMS 3RM W O K I J O K I S E M I C O N D U C T O R GR OU P O K I semiconductor_ r - ? 2 - n -o MSM6569_ _ LCD Dot Matrix Segment Driver TAB GENERAL DESCRIPTION The MSM6569 is a LCD dot m atrix segment driver of a CMOS 1C which consists o f a 160-bit

Contextual Info: CY7C1328G 4-Mbit 256 K x 18 Pipelined DCD Sync SRAM 4-Mbit (256 K × 18) Pipelined DCD Sync SRAM Features Functional Description • Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ❐ Depth expansion without wait state

Contextual Info: CY7C1328G 4-Mbit 256 K x 18 Pipelined DCD Sync SRAM 4-Mbit (256 K × 18) Pipelined DCD Sync SRAM Features Functional Description • Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ❐ Depth expansion without wait state

Contextual Info: CY7C1328G 4-Mbit 256 K x 18 Pipelined DCD Sync SRAM 4-Mbit (256 K × 18) Pipelined DCD Sync SRAM Features Functional Description • Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ❐ Depth expansion without wait state

Contextual Info: CY7C1353G 4-Mbit 256 K x 18 Flow-Through SRAM with NoBL Architecture 4-Mbit (256 K × 18) Flow-Through SRAM with NoBL™ Architecture Features Functional Description • Supports up to 100-MHz bus operations with zero wait states ❐ Data is transferred on every clock

Contextual Info: CY7C1353G 4-Mbit 256 K x 18 Flow-Through SRAM with NoBL Architecture 4-Mbit (256 K × 18) Flow-Through SRAM with NoBL™ Architecture Features Functional Description • Supports up to 100-MHz bus operations with zero wait states ❐ Data is transferred on every clock

FL256

Contextual Info: CY7C1353G 4-Mbit 256 K x 18 Flow-Through SRAM with NoBL Architecture 4-Mbit (256 K × 18) Flow-Through SRAM with NoBL™ Architecture Features Functional Description • Supports up to 100-MHz bus operations with zero wait states ❐ Data is transferred on every clock

Contextual Info: CY7C1353G 4-Mbit 256 K x 18 Flow-Through SRAM with NoBL Architecture 4-Mbit (256 K × 18) Flow-Through SRAM with NoBL™ Architecture Features Functional Description • Supports up to 100-MHz bus operations with zero wait states ❐ Data is transferred on every clock

Contextual Info: CY7C1353G 4-Mbit 256 K x 18 Flow-Through SRAM with NoBL Architecture 4-Mbit (256 K × 18) Flow-Through SRAM with NoBL™ Architecture Features Functional Description • Supports up to 100-MHz bus operations with zero wait states ❐ Data is transferred on every clock

LED BARGRAPH pin configuration

Abstract: 093S b7am display 16 segments 16-SEGMENT 4 digits 7-segment led display cl
Contextual Info: O K I S E MI C O N D U C T O R GROUP 23E D • b75424D DODbSSS b O K I semiconductor_ MSC7110-XX/ MSC7112-xx_ 12-SEGMENT, 16-DIGIT/ 16-SEGMENT, 12-DIGIT GENERAL DESCRIPTION The M SC 7 11 0-xx and M SC 7 11 2-xx are general p urpose display controllers for vacuum fluorescent

Contextual Info: GSD REVISIONS Ca i CN 37541 C REDRAWN JW 01/15/98 CO O NJ CD I O o ho K C -59-545 YRWK DATE CODE KC59545S NOTES* 1. FOR USE WITH RG-59, 62, 71. 140 & 210/U CABLE. 2. FOR CABLING INSTRUCTIONS SEE C P - 1050. 3. INTERFACE PER MIL-STD-348, FIG. 301-1. scale

Sprecher Schuh LE 2-20

Abstract: Sprecher Schuh LE 2-12 Sprecher Schuh le2-12 LE2-20 Sprecher Schuh LE2-20 Sprecher Schuh LE2-16 Sprecher Schuh CT 3-23 LA2-G2853 T3168 Sprecher Schuh L2-16
Contextual Info: Rotary Cam Switches Series L2 Rotary Cam Switches Technical Information K2 K27 Series R-Line Rotary Cam Switches Technical Information K35 K44 Custom Switches K51 K Rotary Cam Switches K1 Series L2 Rotary Cam Switches Sprecher + Schuh’s comprehensive line

A 3120 0504

Abstract: 3144 0842 CKR22BX104K 104 K capacitor CKR22BX392K A 3120 0601 3773 0421 8 DIP 4001 4002 4007 4011 4013 4017 4030 4052 4060 4066 A 3760 0549 MIL-C-39014
Contextual Info: MIL-C-39014/2Pin DIP HOW TO ORDER Military Type Designation: Styles CKR22, CKR23, CKR24 Dash Number Option: MIL-C-39014/22 Add Appropriate Dash Number Part Number Example CKR22 BX 104 K R Style Voltage-Temperature Limits Capacitance Code Capacitance Tolerance

dolby pro logic 2

Abstract: Capacitor 10163 DSP DTS transistor fp 1016 DTV100 STD2000 STV8247 STV8247DSX 100-lr STV8257DSX
Contextual Info: STV8247, STV8257, STV8277, STV8287 Digital audio decoder/processors for A2 and NICAM television/video recorders Features • Full-automatic multi-standard demodulation – B / G / I / L / M / N / D / K standards – Mono AM and FM – FM 2-carrier German and Korean Zweiton