K 351 Search Results

Contextual Info: CY7C1361C, CY7C1363C 9-Mbit 256 K x 36/512 K × 18 Flow-Through SRAM 9-Mbit (256 K × 36/512 K × 18) Flow-through SRAM Functional Description Features • Supports 100 MHz, 133 MHz bus operations ■ Supports 100 MHz bus operations (Automotive) ■ 256 K × 36/512 K × 18 common I/O

Contextual Info: CY7C1361C, CY7C1363C 9-Mbit 256 K x 36/512 K × 18 Flow-Through SRAM 9-Mbit (256 K × 36/512 K × 18) Flow-through SRAM Features Functional Description • Supports 100 MHz, 133 MHz bus operations ■ Supports 100 MHz bus operations (Automotive) ■ 256 K × 36/512 K × 18 common I/O

optocoupler 351

Contextual Info: IL350/351/358/359 Vishay Semiconductors Linear Optocoupler for Optical DAA in Telecommunications, High Performance FEATURES • 2.0 mm high SMD package K 1 8 K A 2 7 A K 3 6 N.C • Low input-output capacitance A 4 5 N.C • Isolation voltage, 3000 VRMS • High sensitivity K1 at low operating LED current

Contextual Info: CY7C1354C CY7C1356C 9-Mbit 256 K x 36/512 K × 18 Pipelined SRAM with NoBL Architecture 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT ■

Diode KD 521 a

Abstract: U106B U106A operational amplifier discrete schematic POWER AMPLIFIER CIRCUIT DIAGRAM 10000 schematics for a PA amplifier CX77301 LMV722 PL19 CLASS diode rf DETECTOR
Contextual Info: APPLICATION NOTE Power Amplifier Control For ETSI 11.10-Compliant Cellular Handsets 1 Simplifying: Introduction Vo KaKs = DSP 1 + K a K s K d K c Controlling the power amplifier in a Global System for Mobile Communications (GSM ) compatible radio is one of the more

proton rx 4000 watts power amplifier circuit diagram

Abstract: Hamamatsu r300 0812E H5783
Contextual Info: PHOTOMULTIPLIER TUBES Basics and Applications THIRD EDITION Edition 3a PHOTON IS OUR BUSINESS 2007 HAMAMATSU PHOTONICS K. K. ▲ Photomultiplier Tubes ▲ Photomultiplier Tube Modules © 2007 HAMAMATSU PHOTONICS K. K. Introduction Light detection technolgy is a powerful tool that provides deeper understanding of more sophisticated

CY7C1355C

Contextual Info: CY7C1355C, CY7C1357C 9-Mbit 256 K x 36 / 512 K × 18 Flow-Through SRAM with NoBL Architecture 9-Mbit (256 K × 36 / 512 K × 18) Flow-through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency™ (NoBL™) architecture eliminates dead

CY7C1355C

Contextual Info: CY7C1355C, CY7C1357C 9-Mbit 256 K x 36 / 512 K × 18 Flow-Through SRAM with NoBL Architecture 9-Mbit (256 K × 36 / 512 K × 18) Flow-through SRAM with NoBL™ Architecture Functional Description Features • No Bus Latency™ (NoBL™) architecture eliminates dead

CY7C1355C

Contextual Info: CY7C1355C, CY7C1357C 9-Mbit 256 K x 36 / 512 K × 18 Flow-Through SRAM with NoBL Architecture 9-Mbit (256 K × 36 / 512 K × 18) Flow-through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency™ (NoBL™) architecture eliminates dead

Contextual Info: CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S PRELIMINARY 16-Mbit 2048 K x 8/1024 K × 16/512 K × 32 nvSRAM Features • 16-Mbit nonvolatile static random access memory (nvSRAM) ❐ 25-ns, 30-ns and 45-ns access times ❐ Internally organized as 2048 K × 8 (CY14X116L),

Contextual Info: CY7C1360C, CY7C1362C 9-Mbit 256 K x 36/512 K × 18 Pipelined SRAM 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM Features Functional Description • Supports bus operation up to 200 MHz ■ Available speed grades: 200, and 166 MHz ■ Registered inputs and outputs for pipelined operation

Contextual Info: iir b -J A B W A K K B B O M F K [M A YO ® K i 8XC51RA/RB/RC CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER Commercial/Express •See Table 1 for Proliferation Options High Performance CHMOS EPROM/ ROM/CPU

Contextual Info: CY14B104LA, CY14B104NA 4-Mbit 512 K x 8/256 K × 16 nvSRAM 4-Mbit (512 K × 8/256 K × 16) nvSRAM Features • Packages ❐ 44-/54-pin thin small outline package (TSOP) Type II ❐ 48-ball fine-pitch ball grid array (FBGA) Pb-free and restriction of hazardous substances (RoHS)

Contextual Info: CY14B104LA, CY14B104NA 4-Mbit 512 K x 8/256 K × 16 nvSRAM 4-Mbit (512 K × 8/256 K × 16) nvSRAM Features • Packages ❐ 44-/54-pin thin small outline package (TSOP) Type II ❐ 48-ball fine-pitch ball grid array (FBGA) Pb-free and restriction of hazardous substances (RoHS)

Contextual Info: CY14B104LA, CY14B104NA 4-Mbit 512 K x 8/256 K × 16 nvSRAM 4-Mbit (512 K × 8/256 K × 16) nvSRAM Features • Packages ❐ 44-/54-pin thin small outline package (TSOP) Type II ❐ 48-ball fine-pitch ball grid array (FBGA) Pb-free and restriction of hazardous substances (RoHS)

ETG81-050

Abstract: 1DI400 1DI400D-100 358 ez 802 ETK81-050 1DI300A-120 1DI200Z-100 1D500A-030 ETK85-050 ID200A-020
Contextual Info: - 237 - m±M. -n F — r BO o- _ k' T i =25°C I S f t r t iE ( V ) Ve E ft A V * . be * (A) (A) * * . t,t. ft k ft * m m R.b 0-0 VK (u s ) T (A) (A) (A) CV) I F k (A) (i¿&) M. k 1p V BE di/dt (A) (V) (A/í/s) * k 2.0 2.5 200 4.0 2.0 12 3.0 4.0 -4.0

eurosil

Abstract: ic tda 6108 tda 9351 SE116 BH 37 933 Eurosil Electronic tfk 635 EL131 TDA 785 LA
Contextual Info: Te m ic TELEFUN KEN Semiconductors Addresses Sales Offices Europe Hungary Sweden T E M IC D a n sk T EM 1C T E L E FU N K E N T E M IC T E L E F U N K E N T E M IC N o rd ic A B c /o A E G D a n s k A k tie s e ls k a b m ic ro e le c tro n ic ìm h H K r u p p s tr a s s e 6

TO247 package rth ambient

Contextual Info: STPS3045C Power Schottky rectifier Datasheet  production data Features A1 • Very small conduction losses K A2  Negligible switching losses  Extremely fast switching A2 A1 K K  Insulated package: TO-220FPAB – Insulating voltage = 2000 V DC – Capacitance = 12 pF

Contextual Info: CY7C1347G 4-Mbit 128 K x 36 Pipelined Sync SRAM 4-Mbit (128 K × 36) Pipelined Sync SRAM Functional Description Features • Fully registered inputs and outputs for pipelined operation ■ 128 K × 36 common I/O architecture ■ 3.3 V core power supply (VDD)

Contextual Info: CY7C1347G 4-Mbit 128 K x 36 Pipelined Sync SRAM 4-Mbit (128 K × 36) Pipelined Sync SRAM Features Functional Description • Fully registered inputs and outputs for pipelined operation ■ 128 K × 36 common I/O architecture ■ 3.3 V core power supply (VDD)

Contextual Info: CY7C1347G 4-Mbit 128 K x 36 Pipelined Sync SRAM 4-Mbit (128 K × 36) Pipelined Sync SRAM Features Functional Description • Fully registered inputs and outputs for pipelined operation ■ 128 K × 36 common I/O architecture ■ 3.3 V core power supply (VDD)

Contextual Info: PRELIMINARY CY14B116K/CY14B116M 16-Mbit 2048 K x 8/1024 K × 16 nvSRAM with Real Time Clock Features Functional Description 16-Mbit nonvolatile static random access memory (nvSRAM) ❐ 25-ns and 45-ns access times ❐ Internally organized as 2048 K × 8 (CY14B116K),

Contextual Info: CY7C1011DV33 2-Mbit 128 K x 16 Static RAM 2-Mbit (128 K × 16) Static RAM Features Functional Description The CY7C1011DV33[1] is a high-performance CMOS Static RAM organized as 128 K words by 16 bits. • Pin-and function-compatible with CY7C1011CV33 ■

Contextual Info: CY7C1364C 9-Mbit 256 K x 32 Pipelined Sync SRAM 9-Mbit (256 K × 32) Pipelined Sync SRAM Features Functional Description • Registered inputs and outputs for pipelined operation ■ 256 K × 32 common I/O architecture ■ 3.3 V core power supply (VDD)