K 351 Search Results

Contextual Info: CY7C1361C, CY7C1363C 9-Mbit 256 K x 36/512 K × 18 Flow-Through SRAM 9-Mbit (256 K × 36/512 K × 18) Flow-through SRAM Functional Description Features • Supports 100 MHz, 133 MHz bus operations ■ Supports 100 MHz bus operations (Automotive) ■ 256 K × 36/512 K × 18 common I/O

Contextual Info: CY7C1361C, CY7C1363C 9-Mbit 256 K x 36/512 K × 18 Flow-Through SRAM 9-Mbit (256 K × 36/512 K × 18) Flow-through SRAM Features Functional Description • Supports 100 MHz, 133 MHz bus operations ■ Supports 100 MHz bus operations (Automotive) ■ 256 K × 36/512 K × 18 common I/O

optocoupler 351

Contextual Info: IL350/351/358/359 Vishay Semiconductors Linear Optocoupler for Optical DAA in Telecommunications, High Performance FEATURES • 2.0 mm high SMD package K 1 8 K A 2 7 A K 3 6 N.C • Low input-output capacitance A 4 5 N.C • Isolation voltage, 3000 VRMS • High sensitivity K1 at low operating LED current

Contextual Info: CY7C1354C CY7C1356C 9-Mbit 256 K x 36/512 K × 18 Pipelined SRAM with NoBL Architecture 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT ■

CY7C1355C

Contextual Info: CY7C1355C, CY7C1357C 9-Mbit 256 K x 36 / 512 K × 18 Flow-Through SRAM with NoBL Architecture 9-Mbit (256 K × 36 / 512 K × 18) Flow-through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency™ (NoBL™) architecture eliminates dead

CY7C1355C

Contextual Info: CY7C1355C, CY7C1357C 9-Mbit 256 K x 36 / 512 K × 18 Flow-Through SRAM with NoBL Architecture 9-Mbit (256 K × 36 / 512 K × 18) Flow-through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency™ (NoBL™) architecture eliminates dead

Contextual Info: CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S PRELIMINARY 16-Mbit 2048 K x 8/1024 K × 16/512 K × 32 nvSRAM Features • 16-Mbit nonvolatile static random access memory (nvSRAM) ❐ 25-ns, 30-ns and 45-ns access times ❐ Internally organized as 2048 K × 8 (CY14X116L),

Contextual Info: CY14B104LA, CY14B104NA 4-Mbit 512 K x 8/256 K × 16 nvSRAM 4-Mbit (512 K × 8/256 K × 16) nvSRAM Features • Packages ❐ 44-/54-pin thin small outline package (TSOP) Type II ❐ 48-ball fine-pitch ball grid array (FBGA) Pb-free and restriction of hazardous substances (RoHS)

Contextual Info: CY14B104LA, CY14B104NA 4-Mbit 512 K x 8/256 K × 16 nvSRAM 4-Mbit (512 K × 8/256 K × 16) nvSRAM Features • Packages ❐ 44-/54-pin thin small outline package (TSOP) Type II ❐ 48-ball fine-pitch ball grid array (FBGA) Pb-free and restriction of hazardous substances (RoHS)

eurosil

Abstract: ic tda 6108 tda 9351 SE116 BH 37 933 Eurosil Electronic tfk 635 EL131 TDA 785 LA
Contextual Info: Te m ic TELEFUN KEN Semiconductors Addresses Sales Offices Europe Hungary Sweden T E M IC D a n sk T EM 1C T E L E FU N K E N T E M IC T E L E F U N K E N T E M IC N o rd ic A B c /o A E G D a n s k A k tie s e ls k a b m ic ro e le c tro n ic ìm h H K r u p p s tr a s s e 6

Contextual Info: CY7C1347G 4-Mbit 128 K x 36 Pipelined Sync SRAM 4-Mbit (128 K × 36) Pipelined Sync SRAM Functional Description Features • Fully registered inputs and outputs for pipelined operation ■ 128 K × 36 common I/O architecture ■ 3.3 V core power supply (VDD)

Contextual Info: CY7C1347G 4-Mbit 128 K x 36 Pipelined Sync SRAM 4-Mbit (128 K × 36) Pipelined Sync SRAM Features Functional Description • Fully registered inputs and outputs for pipelined operation ■ 128 K × 36 common I/O architecture ■ 3.3 V core power supply (VDD)

Contextual Info: PRELIMINARY CY14B116K/CY14B116M 16-Mbit 2048 K x 8/1024 K × 16 nvSRAM with Real Time Clock Features Functional Description 16-Mbit nonvolatile static random access memory (nvSRAM) ❐ 25-ns and 45-ns access times ❐ Internally organized as 2048 K × 8 (CY14B116K),

Contextual Info: CY7C1011DV33 2-Mbit 128 K x 16 Static RAM 2-Mbit (128 K × 16) Static RAM Features Functional Description The CY7C1011DV33[1] is a high-performance CMOS Static RAM organized as 128 K words by 16 bits. • Pin-and function-compatible with CY7C1011CV33 ■

Contextual Info: CY7C1329H 2-Mbit 64 K x 32 Pipelined Sync SRAM 2-Mbit (64 K × 32) Pipelined Sync SRAM Features Functional Description • Registered inputs and outputs for pipelined operation The CY7C1329H SRAM integrates 64 K × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter

cy7c1041dv

Abstract: 10bv CY7C1041DV33
Contextual Info: CY7C1041DV33 4-Mbit 256 K x 16 Static RAM 4-Mbit (256 K × 16) Static RAM Features Functional Description • Temperature ranges ❐ Industrial: –40 °C to 85 °C The CY7C1041DV33 is a high performance CMOS Static RAM organized as 256 K words by 16-bits. To write to the device, take

Contextual Info: CY7C1441AV25 CY7C1447AV25 36-Mbit 1 M x 36/512 K × 72 Flow-Through SRAM 36-Mbit (1 M × 36/512 K × 72) Flow-Through SRAM Functional Description Features • Supports 133 MHz bus operations ■ 1 M × 36/512 K × 72 common I/O ■ 2.5 V core power supply

Contextual Info: CY7C1345G 4-Mbit 128 K x 36 Flow-Through Sync SRAM 4-Mbit (128 K × 36) Flow through Sync SRAM Features Functional Description • 128 K × 36 common I/O ■ 3.3 V core power supply (VDD) ■ 2.5 V or 3.3 V I/O supply (VDDQ) ■ Fast clock-to-output times

CY7C1325G

Contextual Info: CY7C1325G 4-Mbit 256 K x 18 Flow-Through Sync SRAM 4-Mbit (256 K × 18) Flow-Through Sync SRAM Functional Description Features • 256 K × 18 common I/O ■ 3.3 V core power supply (VDD) ■ 2.5 V or 3.3 V I/O power supply (VDDQ) ■ Fast clock-to-output times

Contextual Info: CY7C1381D CY7C1383D, CY7C1383F 18-Mbit 512 K x 36/1 M × 18 Flow-Through SRAM 18-Mbit (512 K × 36/1 M × 18) Flow Through SRAM Features Functional Description • Supports 133 MHz bus operations ■ 512 K × 36 and 1 M × 18 common I/O ■ 3.3 V core power supply (VDD)

Contextual Info: CY7C1325H 4-Mbit 256 K x 18 Flow-Through Sync SRAM 4-Mbit (256 K × 18) Flow-Through Sync SRAM Features Functional Description • 256 K × 18 common I/O ■ 3.3 V core power supply (VDD) ■ 2.5 V or 3.3 V I/O power supply (VDDQ) ■ Fast clock-to-output times

cy7c1441av33-133axi

Abstract: R1136 CY7C1441
Contextual Info: CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 36-Mbit 1 M x 36/2 M × 18/512 K × 72 Flow-Through SRAM 36-Mbit (1 M × 36/2 M × 18/512 K × 72) Flow-Through SRAM Features Functional Description • Supports 133-MHz bus operations ■ 1 M × 36/2 M × 18/512 K × 72 common IO

5024X0

Abstract: T60405-N5024 T60405 t60405n5024x
Contextual Info: DATENBLATT / Specification VACUU M SCHM ELZE K-Nr.: K-no.: 20760 Kunde: T60405-N5024-X056 Datum: Stromkompensierte Drossel / Common Mode Choke Typenelement / Standard type Customer Sach Nr.: 22.03.2006 Date: Kd. Sach Nr.: Seite Customers part no.: Page 1 von 3

ST1230C

Contextual Info: Bulletin I25194 rev. B 01/00 ST1230C.K SERIES PHASE CONTROL THYRISTORS Hockey Puk Version Features 1745A Center amplifying gate Metal case with ceramic insulator International standard case A-24 K-PUK High profile hockey-puk Typical Applications DC motor controls