K 6553 Search Results

DIP42S

Abstract: LC66354B LC66356B LC66358A LC66358B QIP48E
Contextual Info: Ordering number : EN4677 CMOS LSI LC66354B, 66356B, 66358B Four-bit Single-Chip Microcontrollers On-Chip 4 K/6 K/8 K-byte ROM Overview The LC66354B, LC66356B and LC66358B are 42-pin package four-bit CMOS microcontrollers that integrate on a single chip all functions required in a control

HC107

Abstract: CD54HC107 CD54HC107F3A CD74HC107 CD74HC107E CD74HC107M CD74HCT107 HCT10
Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54HC107, CD74HC107, CD74HCT107 Data sheet acquired from Harris Semiconductor SCHS139C Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised May 2003

Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54/74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134C Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised January 2003 Features Description • Hysteresis on Clock Inputs for Improved Noise

Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54/74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134C Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised January 2003 Features Description • Hysteresis on Clock Inputs for Improved Noise

SN75129

Abstract: 1N3064 SN75128 SN751730
Contextual Info: SN75128, SN75129 EIGHT-CHANNEL LINE RECEIVERS SLLS076B – JANUARY 1977 – REVISED MAY 1995 • • • • • • • • • Meets or Exceeds the Requirements of IBM System 360/370 Input/Output Specification Input Resistance . . . 7 kΩ to 20 kΩ

Contextual Info: PCM56P PCM56U DESIGNED FOR AUDIO Serial Input 16-Bit Monolithic DIGITAL-TO-ANALOG CONVERTER FEATURES ● SERIAL INPUT ● –92dB MAX THD: FS Input, K Grade ● –74dB MAX THD: –20dB Input, K Grade ● ● ● ● ● ● ● ● ● ● 96dB DYNAMIC RANGE

Contextual Info: SN54BCT2828B, SN74BCT2828B 10-BIT BUS/MOS MEMORY DRIVERS WITH 3-STATE INVERTING OUTPUTS _ D3635, SEPTEMBER 1990 S N 54B C T282B B . . . J T P A C K A G E BiCMOS Design Substantially Reduces S N 7 4B C T 28 2 8B . . . D W O R N T P A C K A G E

Contextual Info: 54ACT11521, 74ACT11521 8-BIT IDENTITY COMPARATORS S C A S Q 2 3 A - D2957, JU L Y 1978- R E V IS E D A P R I L 1993 54ACT11521 . . . J P A C K A G E 74ACT11521 . . . OB, D W O R N P A C K A G E i * Compares Two 8-Bit Words * Inputs Are TTL-Voltage Compatible

74AC11873

Contextual Info: 54AC11873, 74AC11873 DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS • 54A C 11 8 73 . . . J T P A C K A G E 3-State Buffer-Type Outputs Drive Bus 74AC 11B73 . . . D W OR N T P A C K A G E Lines Directly TOP V IE W • Bus-Structured Pinout • Flow -Through A rchitecture O ptim izes PCB

Contextual Info: 54AC16245, 74AC16245 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS TI0173— D3451, M ARC H 1990 Member of the Texas Instruments Widebus Family 54A C 1 62 4 5 . . . W D P A C K A G E 7 4 A C 16245 . . . D L P A C K A G E TO P V IE W Packaged in Shrink Small Outline 300-mil

Contextual Info: MN101C457 Type MN101C457 ROM x× 8-bit 16 K RAM (×× 8-bit) 0.5 K Package QFP044-P-1010E *Pb free Minimum Instruction Execution Time 0.10 µs (at 4.5 V to 5.5 V, 20 MHz) 0.238 µs (at 2.7 V to 5.5 V, 8.39 MHz) 0.477 µs (at 2.0 V to 5.5 V, 4.19 MHz)* * The lower limit for operation guarantee for EPROM built-in type is 2.7 V.

Contextual Info: 54ACT11874, 74ACT11874 DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS D3447, MAR CH 1990-R E V IS E D O C TO BER 1990 54A C T 11 8 74 . . . J T P A C K A G E Inputs are TTL-Voltage C om patible 74A C T 11 8 74 . . . D W O R N T P A C K A G E

1G1 l

Abstract: D3460
Contextual Info: 54ACT11208, 74ACT11208 DUAL 1-LINE TO 4-LINE CLOCK DRIVERS WITH 3-STATE OUTPUTS _ D3460. AP R IL 1990 54A C T 11 2 08 . . . J P A C K A G E Inputs are TTL-Voltage C om patible 7 4 A C T 11 2 08 . . . D W OR N P A C K A G E Low -Skew Propagation Delay TO P V IE W

Contextual Info: SN55461 THRU SN55463 SN75461 THRU SN75463 DUAL PERIPHERAL DRIVERS SLRS022A - DECEMBER 1976 - REVISED OCTOBER PERIPHERAL DRIVERS FOR HIGH-VOLTAGE, HIGH-CURRENT DRIVER APPLICATIONS S N 5 5 4 6 1 , S N 5546 2, SN 55463 . . . J G P A C K A G E S N 7546 1, S N 7546 2, S N 7546 3 . . O O R P P A C K A G E

D3351

Contextual Info: TIEPAL10H16TE6C TTL-TO-ECLIMPACT-X PAL TRANSLATOR CIRCUIT D3351. OCTOBER 1989 • ECL10H Programmable Logic with TTL-to-ECL Translation JT p a c k a g e TOP VIEW • ECL Control Inputs

Contextual Info: 74ACT11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET _ SCAS064A - D3339. JUNE 1989 - REVISED APRIL 1993 D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Fully Buffered to Offer Maximum Isolation

Contextual Info: User’s Manual µPD77111 Family Digital Signal Processor Architecture µPD77110 µPD77111 µPD77112 µPD77113A µPD77114 µPD77115 Document No. U14623EJ3V0UM00 3rd edition Date Published November 2002 N CP(K) Printed in Japan [MEMO] 2 User’s Manual U14623EJ3V0UM

Contextual Info: User’s Manual µPD98501 Communication Controller Document No. S14767EJ2V0UM00 2nd edition Date Published April 2002 NS CP(K) 1999 2000 Printed in Japan [MEMO] 2 User’s Manual S14767EJ2V0UM SUMMARY OF CONTENTS CHAPTER 1

SLLS008C-D2S31

Abstract: SN75ALS193 d2931 AM26LS32A RS-422-A SN75ALS197
Contextual Info: SN75ALS193 QUAD DIFFERENTIAL LINE RECEIVER WITH 3-STATE OUTPUTS ^ * * * * * * * * * * * _ SLLS008C - D2931, JUNE 1986 - REVISED MARCH 1993 Meets EIA Standards RS-422-A and RS-423-A SN75ALS193 . . . J P A C K A G E t TOP VIEW

V850E/IA1

Abstract: uPD70F3116 cs1m uPD703116 V850E1 86-N RD850 me310 TO-003 DA3 307
Contextual Info: User’s Manual V850E/IA1 32-Bit Single-Chip Microcontrollers Hardware µPD703116 µPD703116 A µPD703116(A1) µPD70F3116 µPD70F3116(A) µPD70F3116(A1) Document No. U14492EJ5V0UD00 (5th edition) Date Published August 2005 N CP(K) 1999, 2002 Printed in Japan

V850E/IA1

Contextual Info: User’s Manual TM V850E/IA1 32-Bit Single-Chip Microcontrollers Hardware µPD703116 µPD703116 A µPD703116(A1) µPD70F3116 µPD70F3116(A) µPD70F3116(A1) Document No. U14492EJ3V0UD00 (3rd edition) Date Published February 2003 N CP(K) Printed in Japan

Contextual Info: SN54F109, SN74F109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDFS047A- MARCH 1987 - REVISED OCTOBER 1993 • Package Options Include Plastic Smali-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs

Contextual Info: SN54ALS112A, SN74ALS112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDAS199A – APRIL 1982 – REVISED DECEMBER 1994 • SN54ALS112A . . . J PACKAGE SN74ALS112A . . . D OR N PACKAGE TOP VIEW Fully Buffered to Offer Maximum Isolation

CD74HCT109MG4

Abstract: CD54HC109F3A CD54HCT109 CD74HC109 CD74HCT109 HC109 C109 CD54HC109
Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Data sheet acquired from Harris Semiconductor SCHS140E Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised October 2003