JK EET Search Results

cq 447

Abstract: 751A-02 511j
Contextual Info: @ m o t o r o l a MC54F/74F114 Product Preview DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP WITH COMMON CLOCKS AND CLEARS) DESCRIPTION — M C54F/74F114 co ntains tw o high-speed JK flip ­ flo p s w ith co m m o n clock and Clear inp u ts. S yn ch ro n o us state

Contextual Info: @ m o to ro la MC54F/74F114 P r o d u c t P r e v ie w DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP WITH COMMON CLOCKS AND CLEARS) DESCRIPTION — MC54F/74F114 contains tw o high-speed JK flipflops w ith com m on clock and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering

Contextual Info: 1 INC._ PA7024 PEEL Array CMOS Programmable Electrically Erasable Logic Array Features Flexible Architecture — Input registers and latches — I/O buried D, T and JK registers with independent clock, preset and reset

Contextual Info: CERAM IC MICROWAVE FILTERS SAW RESONATORS SPECIFICATIONS m u ffn ta /k jK H v to t* im B eet* SAR Series FEATURES • ■ ■ ■ ■ ■ Surface mount or leaded packages Excellent temperature characteristics High stability oscillation High frequency fundamental mode oscillation

Contextual Info: MP7680 DIE J n jk JXJw. 12-Bit Quad Double-Buffered Multiplying Digital-to-Analog Converter CMOS Die Specifications Micro Power Systems ELECTRICAL CHARACTERISTICS Ordering Information Absolute Maximum Ratings TA = 25 C V DD to GND . O V ,+ 7 V

A 222G

Abstract: b 222G
Contextual Info: REV. DESCRIPTION/ECO NO. RELEASED DATE 10/10/08 ELECTRICAL & OPTICAL CHARACTERISTICS JK L PART NUMBER FORWARD FORWARD OPERATING INTENSITY PEAK VOLTAGE DC CURRENT (mA)* TEMP. (C) mcd* WAVELENGTH LED SOURCE LENS TYPE 1/2 ANGLE (DICE) TYPE DEGREE SUPER BRIGHT

Contextual Info: HCTS109T D ata S h eet Ju ly 1999 F ile N u m b er Radiation Hardened Dual JK Flip Flop Features Harris’ Satellite Applications Flow SAF devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard flow intended

Contextual Info: REV. DESCRIPTION/ECO NO. RELEASED 8.6 DATE 10/10/08 27.0 MIN. 1.06" (.339")' 1.0 -0 5 .9 (.232") 1.5 TYP. (.06") (.039") — 2.5 REF. (.10") CATHODE 0 5.0 (.197") □ 0.5 REF. 1.0 MAX. REF. (.039") (. 020 ") ' ELECTRICAL & OPTICAL CHARACTERISTICS JK L PART

Contextual Info: MOTOROLA 0^rN" " “S Semiconductor Components M C10EP35 SO -8, D SUFFIX 8 -L E A D PLASTIC SOIC PACKAGE CASE 751 -06 ORDERING INFORMATION M C10EP35D SOIC Product Preview JK Flip Flop TRUTH TABLE • • • • • • • • • • 300ps Propagation Delay

74F109

Contextual Info: Signetics 74F109 FLIP-FLOP Dual J-K Positive Edge-Triggered Flip-Flops FAST Products DESCRIPTION The 74F109 is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, Clock, Set and Reset inputs; also true and complementary outputs. Set S . and Reset (R ) are asynchronous

PA7024

Contextual Info: INTERNATIONAL C M O S 25E D 4040707 Qoooasa T Preliminary Data INTERNATIONAL CMOS TECHNOLOGY, INC. ''M f e - a -4 "? TM PA7Ö24 PEEL Array CMOS Programmable Electrically Erasable Logic Array Features Flexible Architecture — Input registers and latches — I/O buried D, T and JK registers with

74ls189 ram

Abstract: precon po
Contextual Info: " I — Jk ^ ’g T g ^ 1— mk ^ Page 0001 0 1 /1 6 /8 9 11:16:37 Tx: AM27LS03 TED - Ft: A V O PMT woniNMMSflnncMiMCa Am27LS03 64-Bit Low-Power Inverting-Output Bipolar RAM > 3 ro DISTINCTIVE CHARACTERISTICS Fully decoded 16 word x 4-bit low-power Schottky

WCL 209

Abstract: ltzt
Contextual Info: as DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION The T54LS/T74LS114/114A offer common clock and common clear inputs and individual J, K, and set inputs. These monolithic dual flip-flops are de­ signed so that when the clock goes HIGH, the in­ puts are enabled and data will be accepted. The

Contextual Info: M M O T O R O L A MC54F113 MC74F113 Advance Information DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION — MC54F/74F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs

Contextual Info: ADVANCE INFORMATION AM A M All inform ation in this data sheet is prelim inary and su b je ct to change. AM j Æ w W u jÆ M Jk AMAM jÆ w W w 8/93 5-Tap Silicon D elay Line _ G e n e ra l D e s c rip tio n The M XD1000 silicon delay line has five equally spaced

74LS

Abstract: LS195A
Contextual Info: Am25LS194A • Am54LS/74LS194A Am25LS195A • Am54LS/74LS195A Four-Bit High-Speed Shift Registers D IS T IN C T IV E C H A R A C T E R IS T IC S • • • • • L O G IC D IA G R A M S S h ift rig h t o r parallel load w ith JK in p u ts on A m 2 5 L S 1 9 5 A

10990

Abstract: MS-022
Contextual Info: R E V 1 S 1O N S LTR •31.2+0.4 TYP - 96 DESCRIPTION A R ELEA SE B REV NOTE 4 ; 3 .4 0 TOL WAS 0 . 0 2 ; 0° •7*WAS 0° -1 0 ° ; 0 .2 0 MIN WAS 0 .4 0 TO DOCUMENT C O N T R O L. MIN E .C .N . DATE 10357 0 3 /2 9 /9 4 D E G / H JK BY/APP'D 10990 0 6 /0 6 /9 5

subminiature 5783

Abstract: electronic 40 w tube light circuit CK5783WA Raytheon Company centrifuge industrial tube company subminiature tubes 5783WA
Contextual Info: TECHNICAL INFORMATION RELIABLE SUBMINIATURE GAS DIODE TYPE JK — C. ¿ -L L . S jL CK 5 7 8 3 W A T he CK5783W A is a c o ld -c a th o d e , gas f ille d , g lo w -d is c h a rg e diod e o f sub m iniatu re c o n s tru c tio n designed fo r use as a v o lta g e re fe re n ce tu b e in e le c tro n ic a lly re g u la te d dc power s u p p lie s .

Contextual Info: PICK AND PLACE PAD NOTES: 1- SHIELD M ATERIAL GERMAN SILVER 0.20mm THICK CuNI18 Z n 2 0 HV 180-210 2 - HOUSING M ATERIAL: LCP COLOR: BLACK 3 - CONTACT M ATERIAL: C uSn6 PLATING: SEE SH EET 3 4 - PACKAGING SPEC. P K -8 5 3 4 9 -0 0 4 5.20 0.8 TYP. TYP. 11.9+l

Motorola u

Contextual Info: MOTOROLA U K . DUAL J-K MASTER-SLAVE FLIP-FLOP The MC10135 is a dual master-slave dc coupled J-K flip-flop. Asynchronous set S and reset (R )are provided. The set and reset inputs override the clock. _ A com mon clock is provided with separate J-K inputs. When

Contextual Info: MOTOROLA DUAL J-K MASTER SLAVE FLIP-FLOP L SUFFIX CERAMIC PACKAGE CASE 620 T h e M C 1 0 H 1 3 5 is a dual J-K m aster slave flip -flo p . T h e device ¡s pro vid ed w ith an asy nchronou s set s and reset{R). These set and reset inputs ove rid e th e clock.

TI0103

Contextual Info: 54ACT11112, 74ACT11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET T I0103— D 3339, JUNE 1989— REVISED JAN U AR Y 1990 • Inputs are TTL-Voltage Compatible 54ACT11112 . . . J PACKAGE 74ACT11112 . . . D OR N PACKAGE Flow-Through Architecture to Optimize PCB

Contextual Info: 3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET, 5 VOLT TOLERANT I/O FEATURES: - DESCRIPTION: 0 .5 M IC R O N C M O S T e c h n o lo g y E S D > 2 0 0 0 V p e r M IL -S T D -8 8 3 , M e th o d 301 5; > 2 0 0 V u s in g m a c h in e m o d e l C = 2 0 0 p F , R = 0

Contextual Info: DRAW ING MADE THIS IN DRAW ING T H IR D IS 7 A N G LE P R O JE C T IO N U N P U B L IS H E D . AMP RELEA SED 2 LÛC FO R P U B L IC A T IO N AD 39 CO PYRIG HT 19 BY INCORPORATED,HARR IS B U R G , PA . ALL INTERNA TIONAL R IG H T S R E SER V ED . PRODUCTS MAY B E COVERED BY