JESD78 REVISION E Search Results

VCC-1500

Abstract: VCC-760 8 way flip-flop ic MC100ES6030 MC100ES6030DW MC100ES6030DWR2 MC100ES6030EG
Contextual Info: 3.3V ECL Triple D Flip-Flop w/Set and Reset MC100ES6030 DATA SHEET The MC100ES6030 is a triple master-slave D flip-flop with differential outputs. When the clock input is low, data enters the master latch and transfers to the slave during a positive transition on the clock input.

Contextual Info: 3.3V ECL Triple D Flip-Flop w/Set and Reset MC100ES6030 DATA SHEET Product Discontinuance Notice – Last Time Buy Expires on 12/7/2013 The MC100ES6030 is a triple master-slave D flip-flop with differential outputs. When the clock input is low, data enters the master latch and transfers to the slave during a positive

Contextual Info: MAX14566BE RELIABILITY REPORT FOR MAX14566BEETA+ PLASTIC ENCAPSULATED DEVICES March 1, 2011 MAXIM INTEGRATED PRODUCTS 120 SAN GABRIEL DR. SUNNYVALE, CA 94086 Approved by Sokhom Chum Quality Assurance Reliability Engineer Maxim Integrated Products. All rights reserved.

Contextual Info: 3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Translator MC100ES60T22 Product Discontinuance Notice – Last Time Buy Expires on 12/12/2013 The MC100ES60T22 is a low skew dual LVTTL/LVCMOS to differential LVPECL translator. The low voltage PECL levels, small package, and dual gate

MC100ES6535

Abstract: MC100ES6535DT MC100ES6535DTR2 TSSOP-20
Contextual Info: 3.3V LVCMOS-to-LVPECL 1:4 Fanout Buffer MC100ES6535 DATA SHEET The MC100ES6535 is a low skew, high performance 3.3 V 1-to-4 LVCMOS to LVPECL fanout buffer. The ES6535 has two selectable inputs that allow LVCMOS or LVTTL input levels which translate to LVPECL outputs. The clock enable is internally synchronized to eliminate

Contextual Info: 3.3V Dual Differential LVPECL to LVTTL Translator MC100ES60T23 DATASHEET PRODUCT DISCONTINUANCE NOTICE - LAST TIME BUY EXPIRES ON 2/3/13 3.3 V Dual Differential LVPECL to LVTTL Translator The MC100ES60T23 is a dual differential LVPECL-to-LVTTL translator. The

capacitor cross reference

Abstract: Integrated Device Technology CROSS
Contextual Info: 2.5V, 3.3V ECL/LVPECL/LVDS Dual Differential 2:1 Multiplexer MC100ES6056 NRND DATASHEET NRND – Not Recommend for New Designs Product Discontinuance Notice – Last Time Buy Expires on 12/23/2013 The MC100ES6056 is a dual, fully differential 2:1 multiplexer. The differential data path

capacitor cross reference

Abstract: Integrated Device Technology CROSS
Contextual Info: 2.5V, 3.3V ECL/LVPECL/LVDS Dual Differential 2:1 Multiplexer MC100ES6056 NRND DATASHEET NRND – Not Recommend for New Designs The MC100ES6056 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals.

JESD22-A114

Abstract: JESD22-A115 JESD78 PCA9544A PCA9558 PCA9558PW PCA9558PW-T PCA9588
Contextual Info: NXP 6-bit I2C-bus DIP switch with integrated 8-bit GPIO and 2K EEPROM Multi-function I2C-bus device simplifies board configuration Equipped with a multiplexed EEPROM, an I/O expander, and a write-protected serial EEPROM, this highly integrated device makes it easy to implement a variety of functions.

JESD78

Contextual Info: DG90LV011 Vishay Siliconix 3V High Speed Single LVDS Driver DESCRIPTION The DG90LV011 High Speed driver is optimized for data rate in excess of 400 Mbps 200 MHz . Device works under current mode. It conforms to TIA/EIA standard. It is designed and manufactured for industrial temperature (- 40 °C ~ 85 °C) applications.

MAX14566E

Contextual Info: MAX14566E RELIABILITY REPORT FOR MAX14566EETA+T PLASTIC ENCAPSULATED DEVICES April 14, 2011 MAXIM INTEGRATED PRODUCTS 120 SAN GABRIEL DR. SUNNYVALE, CA 94086 Approved by Richard Aburano Quality Assurance Manager, Reliability Operations Maxim Integrated Products. All rights reserved.

NXP MARK

Contextual Info: GTL2018 8-bit LVTTL to GTL transceiver Rev. 2 — 29 August 2011 Product data sheet 1. General description The GTL2018 is an octal translating transceiver designed for 3.3 V LVTTL system interface with a GTL/GTL/GTL+ bus. The direction pin DIR allows the part to function as either a GTL-to-LVTTL sampling

Contextual Info: GTL2018 8-bit LVTTL to GTL transceiver Rev. 2 — 29 August 2011 Product data sheet 1. General description The GTL2018 is an octal translating transceiver designed for 3.3 V LVTTL system interface with a GTL/GTL/GTL+ bus. The direction pin DIR allows the part to function as either a GTL-to-LVTTL sampling

ES603

Contextual Info: 3.3V ECL/PECL/HSTL/LVDS ÷2/4, ÷4/6 Clock Generation Chip MC100ES6039 Product Discontinuance Notice – Last Time Buy Expires on 12/19/2013 The MC100ES6039 is a low skew 2/4, 4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each

JESD22-B117

Abstract: Latch up test JESD78 JESD22-B111 DTS04169EN DTS04193EN JEDEC JESD22-B117 dts04193 QLT POWER IEC-68-2-21 JESD78
Contextual Info: RF6280 Qualification Report Page 1 of 2 QLT-01087, Revision B Product Description A multi-functional power management unit DC‐DC converter Package Type WLCSP, 2 x 2 x 0.65 mm Process Technology Si Qualification # 06‐QUAL‐752 Date Issued

Contextual Info: 2.5/3.3V 1:4 PECL Clock Driver with 2:1 Input MUX MC100ES6130 DATASHEET Product Discontinuance Notice – Last Time Buy Expires on 12/7/2013 The MC100ES6130 is a 2.5 GHz differential PECL 1:4 fanout buffer. The ES6130 offers a wide operating range of 2.5 V and 3.3 V and also features a 2:1 input MUX

Contextual Info: Low Voltage 1:5 Differential LVDS Clock Fanout Buffer MC100ES8014 Product Discontinuance Notice – Last Time Buy Expires on 1/31/2014 Product Preview DATASHEET MC100ES8014 The MC100ES8014 is a HSTL differential clock fanout buffer. Designed for the most demanding clock distribution systems, the MC100ES8014 supports

JESD22-A110

Abstract: JESD22-A104 JESD22A110 Latch up test JESD78 A104 diode JESD22-A115 transistor C101 JESD22-A108 IEC 68-2-21 JESD22-A114
Contextual Info: RF1450 Qualification Report Page 1 of 2 QLT-02952, Revision A Product Description Package Type Broadband High Power SP4T Switch QFN Process Technology GaAs, Si Date Issued 4/23/08 3mm x 3mm x 0.85mm Qualification # 07-Qual-922 FOR IMPORTANT INFORMATION REGARDING THESE MATERIALS INCLUDING DISCLAIMERS REGARDING USE IN CERTAIN

SMDJ-65609EV-40SR

Abstract: QML-38535 MIL-PRF38535 5962-0250101VXC
Contextual Info: REVISIONS LTR DESCRIPTION DATE YR-MO-DA A Corrected L dimension for case outline X, RHA editorial information added to selected paragraphs. ksr B Corrected 1.3 Power dissipation from 1W to 0.2W; Thermal resistance junction to case from 10°C/W to 14°C/W; added ICCDR,TCDR, and TR to

DG2750

Abstract: DG2750DN-T1-E4 HP4192A JESD78
Contextual Info: DG2750 Vishay Siliconix Low Voltage Dual SPDT Analog Switch with Negative Swing Audio Capability DESCRIPTION FEATURES The DG2750 is a dual SPDT low on-resistance switch designed to from a single 1.8 V to 5.0 V power supply. It is a bi-directional switch, and is capable of switching negative

74ABT821N

Abstract: 74ABT374A 74ABT534A 74ABT821 74ABT821D 74ABT821DB 74ABT821PW JESD78 SO24
Contextual Info: 74ABT821 10-bit D-type flip-flop; positive-edge trigger; 3-state Rev. 02 — 12 April 2005 Product data sheet 1. General description The 74ABT821 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.

ZY 22 1D6

Abstract: 74LVT162374 74LVT162374DGG 74LVT162374DL JESD78 SSOP48 TSSOP48
Contextual Info: 74LVT162374 3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω termination resistors; 3-state Rev. 03 — 17 January 2005 Product data sheet 1. General description The 74LVT162374 is a high performance BiCMOS product designed for VCC operation at 3.3 V.

aircraft logic gates

Abstract: 74LVT574 74LVT574D 74LVT574DB 74LVT574PW 74LVTH574 74LVTH574D 74LVTH574PW JESD78 SO20
Contextual Info: 74LVT574; 74LVTH574 3.3 V octal D-type flip-flop; 3-state Rev. 03 — 23 March 2006 Product data sheet 1. General description The 74LVT574; 74LVTH574 is a high-performance BiCMOS product designed for VCC operation at 3.3 V. This device is an 8-bit, edge triggered register coupled to eight 3-state output buffers. The

IDT7204L30TDB

Abstract: IDT7204L30DB qml-38535
Contextual Info: REVISIONS LTR DESCRIPTION DATE YR-MO-DA APPROVED C Update boilerplate of document. Add devices 06 and 07. Add vendor CAGE 61772 as source of supply for devices 06 and 07. Editorial changes throughout. 93-11-15 M. A. Frye D Changes in accordance with NOR 5962-R187-95