IPS BD Search Results

Contextual Info: Datasheet 2ch IPS Intelligent Power Switch BDS2DJ22GUL（Two channel /3.6V/200mA） ●General Description BDS2DJ22GUL is an intelligent power switch IC (IPS) that has two built-in N-channel MOSFETs capable of carrying 200mA current. This switch IC operates from low input voltages from 1.0V to 3.6V and exhibits a typical on-resistance of 45 mΩ.

Contextual Info: Datasheet 2ch IPS Intelligent Power Switch BDS2DJ22GUL（Two channel /3.6V/200mA） ●General Description BDS2DJ22GUL is an intelligent power switch IC (IPS) that has two built-in N-channel MOSFETs capable of carrying 200mA current. This switch IC operates from low input voltages from 1.0V to 3.6V and exhibits a typical on-resistance of 45 mΩ.

1AD4

Abstract: ADSP-2186M ADSP-2100 Family EZ-Tools data sheet lsd 3010 A0-A21 ADSP-2100 ADSP-2181 DL195
Contextual Info: ANALOG DSP devices _ Microcomputer □ Preliminary Technical Data ADSP-2186M FEATURES Performance 13.3 ns Instruction Cycle T im e @ 2.5 Volts internal , 75 M IPS Sustained Perform ance Single-Cycle Instruction Execution Single-Cycle C ontext Switch

dct 814

Abstract: clock tree balancing IC 2073 astro tools B2008 project ips ips works astro mb HIERARCHICALLY astro place and routing
Contextual Info: Designing Hierarchically Reusable Digital IPs Using DC-T/ICC Flow James Deng Michael Lai Ninh Ngo Keith Duwel Kevin Huang Michael Zheng Richard Price Altera Corporation San Jose, California, USA www.altera.com Liang Xu, Sridhar Panchapakesan, Pallavi Padala

evelo

Contextual Info: ANALOG DEVICES DSP Microcomputer AD6F-2186L FEATURES PERFORMANCE 30 ns Instruction Cycle Time 33 M IPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle

Contextual Info: ANALOG DEVICES FEATURES PERFORMANCE 30 ns Instruction Cycle Tim e 33 M IPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture A llow s Dual Operand Fetches in Every Instruction Cycle M ultifunction Instructions

CQ 4.000 crystal oscillator 4Mhz

Abstract: 80C51 80C58 87C58 8XC58 SU00185
Contextual Info: INTEGRATED CIRCUITS 80C58/87C58 CMOS single-chip 8-bit microcontrollers Preliminary specification 1995 Feb 02 IC20 ips Semiconductors PHILIPS P H IL IP S 7110ABLj 00A747B 57 b • \ Philips Sem iconductors Prelim inary specification CMOS single-chip 8-bit microcontrollers

Contextual Info: IPS 1. E, 3. 4. 5. MIA FIBRE CHANNEL CABLE CHARACTERISTIC DIFFERENTIALIMPEDANCE 150A ±100 MAXIMUM SKEW BETWEEN CDNDUCTDRS IN A PAIR SOOpsec ND CDNTACTS IN PDSITIDN 4 ASSEMBLY TD BE LABELLED AS FDLLDWS BDTH ENDS>i "P a rt N um ber” REV.’ïe v e l" "YrWk"

Contextual Info: a FEATURES PERFORM ANCE 25 ns Instruction Cycle Time from 20 M Hz Crystal @ 5.0 Volts 40 M IPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Sw itch 3-Bus Architecture Allow s Dual Operand Fetches in Every Instruction Cycle

Contextual Info: FACTSHEET F-199 amtec INTERCONNECT STR IPS S E slIS, Mates with: ♦ Choice of precision machined BXX Series or coined (LBS Series) lerm inals ♦ Approach fhe reliability of a perm anent connection with the flexibility of a separable connection Specifications:

Contextual Info: Introduction The V r 4100 microprocessor is a low-cost, low-power microprocessor that is compatible with the M IPS I, MIPS II, and MIPS III Instruction Set Architecture ISA , except for the Floating-point operating instructions, LL/LLD instruction and SC/SCD instruction.

GV6000

Abstract: D2-3554 TorqProve encoder ROD 431 24vdc motor forward reverse control diagram P320 P323 VHZ 454 Flowserve reliance GV6000 MANUAL
Contextual Info: IPS Tempo Application Manual Instruction Manual D2-3554 The information in this manual is subject to change without notice. Throughout this manual, the following notes are used to alert you to safety considerations: ! ATTENTION: Identifies information about practices or circumstances that can lead to personal

VFD 818 B2 P2

Abstract: transformer inverter ips 12v chopper transformer ips diagram 12vdc motor forward reverse control diagram D2-3554 KP-446 D2-3553-1 diagram LG LCD TV circuits 230 DC variable speed control MPS 726
Contextual Info: IPS Tempo User Manual Instruction Manual D2-3553-1 The information in this manual is subject to change without notice. Throughout this manual, the following notes are used to alert you to safety considerations: ! ATTENTION: Identifies information about practices or circumstances that can lead to personal

0x2000a

Contextual Info: ANALOG DEVICES □ Preliminary Technical Data DSP Microcomputer ADSP-2189M FEATURES Performance 13.3 ns Instruction Cycle Tim e @ 2.5 Volts internal , 75 M IPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle C ontext Switch 3-Bus A rchitecture Allows D ual O perand Fetches in Every Instruction Cycle

Contextual Info: SLVU748 – August 2012 Using the TPS84259: Negative Output Voltage, up to 15-W, Integrated Power Solution EVM Introduction The TPS84259EVM-001 Evaluation Module is designed as an easy-to-use platform that facilitates an extensive evaluation of the features and performance of the Integrated Power Solution IPS device. This

Contextual Info: a FEATURES PERFORM ANCE 30 ns Instruction Cycle Time 33 M IPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Sw itch 3-Bus Architecture Allow s Dual Operand Fetches in Every Instruction Cycle M ultifunction Instructions Pow er-Dow n M ode Featuring Low CM OS Standby

Contextual Info: F-207 IN TER C O N N EC T STR IPS BBD “ s&»Bt» HS BDL SERIES M a te s w ith : TYPE STRIP SS, SD, HSS, SL, SDL, ESS, ESD H U 1 I NO. PINS M I PER ROW U PLATING M OPTION U LEAD STYLE FEATURES • Low profile design achieves 3,89mm .153" board spacings

Contextual Info: F-207 IN TER C O N N EC T STR IPS BBD “ s&»Bt» HS BDL SERIES M ates with: TYPE STRIP SS, SD, HSS, SL, SDL, ESS, ESD H U 1 I NO. PINS M I PER ROW U PLATING M OPTION U LEAD STYLE FEATURES • Low profile design achieves 3,89mm .153" board spacings when mated with SL

Contextual Info: F-206-1 IN TER C O N N EC T STR IPS BBD “ s&»Bt» HS BDL SERIES M a te s w ith : TYPE STRIP SS, SD, HSS, SL, SDL, ESS, ESD H U 1 I NO. PINS M I PER ROW U PLATING M OPTION U LEAD STYLE FEATURES • Low profile design achieves 3,89mm .153" board spacings

Contextual Info: F-206-1 IN TER C O N N EC T STR IPS BBD “ s&»Bt» HS BDL SERIES M ates with: TYPE STRIP SS, SD, HSS, SL, SDL, ESS, ESD H U 1 I NO. PINS M I PER ROW U PLATING M OPTION U LEAD STYLE FEATURES • Low profile design achieves 3,89mm .153" board spacings when mated with SL

Contextual Info: L- -4P,4 [1 ,6 7 ']- -100,0 [3 ,9 4 '] -205,00 [8,071]- Transmit F2 -50,0 [1.97'J 0W 7,62 [0,300'] Receive II 3 1 IPS 2 1 # 4 /4 0 S ta n d D f f 's 3,23 [0,127'] * J - -50,0 [1 ,9 7 ']- 1. 2. 3. 4. 30AWG 1 5 0 0 SHIELDED PARALLEL PAIR CABLE

PLE3-12

Abstract: program altera ep320 altera ep320 EP1800 ep320 Altera EP1800 Altera ep310 EPB2001JC altera ep900 EP1210 44
Contextual Info: U S E R -C O N F IG U R A B L E A D A P TER IN TER FA C E C H IPS EPB2001 FOR P S ;2 M IC R O C H A N N E L EPB2002 FEATURES User-C onfigurable Adapter Interface Chip Set for PS/2 M icro Channel Bus Add-O n Boards: EPB2001 Single-Chip Adapter Interface Device

epb2001 altera

Contextual Info: U S E R -C O N F IG U R A B L E A D A P T E R IN TER FA C E C H IPS EPB2001 FOR PS 2 M IC R O C H A N N E L EPB2002 FEATURES User-C onfigurable Adapter Interface Chip Set for PS/2 Micro Channel Bus Add-O n Boards: EPB2001 Single-Chip Adapter Interface Device

f 4556

Abstract: TRANSISTOR BD 137-10 329 9148 lg 8993
Contextual Info: CDQ0303-QS UPP@š•@VPPP@mh¡ d›„’L@u’š˜„@l•ž@n•Œ ˆL@hŒŠ‹@ipS@a“–’Œ‰Œˆ˜ mŒ“ŒŸ@b˜•„‡…„”‡L@i”†N@QPWYU@r•†‘’ˆ @r‡NL@h•›™š•”L@tˆŸ„™@WWPYY †•“