INTEL 82355 Search Results

intel 82350

Abstract: architecture of 80486 microprocessor EISA chip set isa bus master 386 intel 8742 intel 82357 intel 82352 82352 intel 82358
Contextual Info: 82350 will need to run four cycles to the 8-bit slave and route the bytes to appropriate byte lanes EISA TERMINOLOGY ISA BU S— The bus used in Industry Standard Archi­ tecture compatible computers. In the context of an E IS A system, it refers to the ISA subset of the E IS A

XC90

Contextual Info: in tj 82355 BUS MASTER INTERFACE CONTROLLER BMIC • Designed for use in 32-Bit EISA Bus Master Expansion Board Designs — Integrates Three Interfaces (EISA, Local CPU, and Transfer Buffer) ■ Supports 16- and 32-Bit Burst Transfers — 33 Mbytes/Sec Maximum Data

intel 82350

Abstract: intel 82352 82351 eisa intel 82357 intel 82358 82359 82350DT EISA Chip Set Design Guide 2LF 1418 82350DT
Contextual Info: in te i 82358DT EISA Bus Controller • Supports 82350 and 82350DT Chip Set Based Systems — Mode Selectable for Either 82350 or 82350DT Based Systems — Mode Defaults to 82350 Based Systems ■ Socket Compatible with the 82358 EISA Bus Controller ■ Provides EISA/ISA Bus Cycle

XC90

Abstract: intel 82358
Contextual Info: 82355 BUS MASTER INTERFACE CONTROLLER BMIC • Designed for use in 32-Bit EISA Bus Master Expansion Board Designs — Integrates Three interfaces (EISA, Local CPU, and Transfer Buffer) ■ Supports 16- and 32-Bit Burst Transfers — 33 Mbytes/Sec Maximum Data

Contextual Info: BROOKTREE CORP b3E B • 1^455^5 DDQ7G3T Interface Specification IS-210.15 SMDS C o n tro l and R e a sse m b ly F o r m a tte r Part # UGA-210 M arch, 1993 Brooktree Brooktree Corporation 9950 Barnes Canyon Road San Diego, CA 92121 USA 6 1 9 -4 5 2 -7 5 8 0

82358

Abstract: XC96 8251 intel microcontroller architecture F245B intel 82358 INTERFACING OF 8272 WITH 8086 EISA chip set 82355 ta 8271 hq intel 82355
Contextual Info: 82355 BUS MASTER INTERFACE CONTROLLER BMIC • Designed fo r use in 32-Bit EISA Bus Master Expansion Board Designs — Integrates Three interfaces (EISA, Local CPU, and Transfer Buffer) ■ Supports 16- and 32-Bit Burst Transfers — 33 M b ytes/S ec Maximum Data

stk 3120

Abstract: 80c186 obsolete date CR056 DT 8210 IC TSC 232 CPE cr038 DT 8210 stk 432 070 BT8210EPF 8210 microprocessor
Contextual Info: Advance Information This document contains information on a product under development. The parametric information contains target parameters that are subject to change. Printed exclusively for DataRace Bt8209/8210 SMDS Control and Reassembly Formatter SCARF

rsm 2814

Contextual Info: 1.0 Product Description - The Bt8209 and Bt8210 Switched Multimegabit Data Service SMDS Control and Reassembly Formatters (SCARF) provide a single-access SMDS service ter­ mination for connectionless data, “datagram,” transfer according to Bellcore TRTSV-000772 and TR-TSV-000773. Customer Premise Equipment (CPE) and