INSTRUCTION SET PROCESSOR INTEL Search Results

Contextual Info: intel APPENDIX A INSTRUCTION SET REFERENCE This appendix provides reference information for the instruction set of the family of MCS 96 microcontrollers. It defines the processor status word PSW flags, describes each instruction, shows the relationships between instructions and PSW flags, and shows hexadecimal opcodes,

Contextual Info: In te l MILITARY Intel386 HIGH PERFORMANCE 32-BIT MICROPROCESSOR WITH INTEGRATED MEMORY MANAGEMENT • Flexible 32-Bit Microprocessor — 8, 16, 32-Bit Data Types — 8 General Purpose 32-Bit Registers ■ Very Large Address Space — 4 Gigabyte Physical

Intel overdrive

Contextual Info: in t e i Intel486 SX M ICROPROCESSOR IM PORTANT— Read This Section Before Reading The Rest Of The Data Sheet This data sheet describes the Intel486 SX microprocessor, the Intel OverDrive™ Processor, and the l n t e l 4 8 7 TM S X Math Coprocessor. All normal text describes the functionality for the Intel486 SX microproces­

Contextual Info: in te l CHAPTER 7 FLOATING-POINT UNIT The Intel Architecture Floating-Point Unit FPU provides high-performance floating-point processing capabilities. It supports the real, integer, and BCD-integer data types and the floating­ point processing algorithms and exception handling architecture defined in the IEEE 754 and

IC GE 6066

Contextual Info: Intel386 SX MICROPROCESSOR • Full 32-Bit Internal Architecture — 8-, 16-, 32-Bit Data Types — 8 General Purpose 32-Bit Registers ■ Runs ln te l 3 8 6 TM Software in a Cost Effective 16-Bit Hardware Environment — Runs Same Applications and O.S.’s

Contextual Info: 5hE D • M fl2bl7S INTEL 011M07S CORP 402 ■ IT L 1 U P/PR PH LS 80960KA EMBEDDED 32-BIT PROCESSOR ■ Built-In Interrupt Controller — 32 Priority Levels 256 Vectors — 3.4 jlis Latency @ 25 MHz _ Easy to Use, High Bandwidth 32-Bit Bus — 66.7 Mbytes/s Burst

Contextual Info: PIE5@ y T [p[^E¥00 in te l Military lntel386TM EX EMBEDDED MICROPROCESSOR • Static Intel386 CPU Core — Low Power Consumption — 5V ± 5% Operating Power Supply — 25 MHz Operating Frequency Large Uniform Address Space — 64 Megabyte Physical — 64 Terabyte Virtual

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Abstract: intel 80186 pin out 80186
Contextual Info: INTEL CORP in t@ UP/PRPHLS 31E D • 4fi5fql7S OCHlSTfc, 3 ■ T 7 - - V 9 - / 7- 80186 HIGH INTEGRATION 16-BIT MICROPROCESSOR ■ Integrated Feature Set — Enhanced 8086-2 CPU — Clock Generator — 2 Independent DMA Channels — Programmable Interrupt Controller

Contextual Info: in t e i MILITARY i486 MICROPROCESSOR Binary Compatible with Large Software Base -M S -D O S *, O S /2*, Windows — U NIX* System V/386 — iRMX , iRM KTM Kernels Easy To Use — Built-In Self Test — Hardware Debugging Support — Intel Software Support

Contextual Info: M S W A M G IS O M F C Q M Ä Y I M Intel386 SXSA EMBEDDED MICROPROCESSOR • Static lntel3 8 6 TM CPU Core — Low Power Consumption — Operating Power Supply 4.5V to 5.5V— 25 MHz and 33 MHz 4.75V to 5.25V— 40 MHz — Operating Frequency SA-40 = 40 MHz

Contextual Info: Intel 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Dem ultiplexed 32-bit Burst Bus with Pipelining • 32-bit Parallel Architecture — Two Instructions/clock Execution

Contextual Info: in y CHAPTER 6 INSTRUCTION SET REFERENCE This chapter provides detailed information about each instruction available to the i960 Jx processors. Instructions are listed alphabetically by assembly language mnemonic. Format and notation used in this chapter are defined in section 6.1, “NOTATION” pg. 6-1 .

Pentium A80501-60

Contextual Info: in te i PENTIUM PROCESSOR Max. Operating Frequency 75 MHz 90 MHz 100 MHz 120 MHz 133 MHz 150 MHz 166 MHz 200 MHz 67 81 90 100 111 114 127 142 iCOMP* Index 2.0 Rating Note: Contact Intel Corporation for more information about iCOMP*lndex 2.0 ratings. Compatible with Large Software Base

Contextual Info: in te i PENTIUM PROCESSOR Max. Operating Frequency 75 MHz 90 MHz 100 MHz 120 MHz 133 MHz 150 MHz 166 MHz 200 MHz 67 81 90 100 111 114 127 142 iCOM P* Index 2.0 Rating Note: Contact Intel Corporation for more information about iCOMP®lndex 2.0 ratings. Com patible with Large Softw are Base

Contextual Info: User’s Manual µPD98501 Communication Controller Document No. S14767EJ2V0UM00 2nd edition Date Published April 2002 NS CP(K) 1999 2000 Printed in Japan [MEMO] 2 User’s Manual S14767EJ2V0UM SUMMARY OF CONTENTS CHAPTER 1

CNF11

Contextual Info: TMS320F206 DIGITAL SIGNAL PROCESSOR SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998 D D D High-Performance Static CMOS Technology Includes the T320C2xLP Core CPU TMS320F206 is a Member of the TMS320C20x Generation, Which Also Includes the TMS320C203, and

Contextual Info: in te i 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped

Contextual Info: intei 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Military On-Chip Memory Management Unit — 4 Gigabyte Virtual Address Space per Task — 4 Kbyte Pages with Supervisor/User Protection High-Performance Embedded

TDA 11136 PS

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Contextual Info: AGWAKKSS 0 MF [F3G!MYO®(i! MILITARY ¡386 SX MICROPROCESSOR • Full 32-Bit Internal Architecture - 8 - , 16-, 32-Bit Data Types — 8 General Purpose 32-Bit Registers ■ Virtual M8086 Mode Allows Execution of M8086 Software in a Protected and Paged System

Contextual Info: in te i JAN 3 ölMföRfflÄTTO «] 80C287A CHMOS III MATH COPROCESSOR High Performance 80-Bit Internal Architecture Implements ANSI/IEEE Standard 7541985 for Binary Floating-Point Arithmetic Implements Extended 80387 Instruction Set Directly Extends CPU’s Instruction Set

Contextual Info: in t e i M80C187 80-BIT NUMERIC PROCESSOR EXTENSION Military High Performance 80-Bit Internal Architecture Two to Three Times M8087 Performance at Equivalent Clock Speed Implements ANSI/IEEE Standard 7541985 for Binary Floating-Point Arithmetic Upward Object-Code Compatible from

Contextual Info: 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING POINT UNIT • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ Built-In Interrupt Controller — 31 Priority Levels, 256 Vectors

Phoenix BIOS manual f.34

Abstract: Phoenix BIOS f.34 manual dSMC Phoenix BIOS user manual f.34 acadia Cyrix 486 Cyrix 6x86mx 243192 diode T35 12H stamford voltage regulator
Contextual Info: Preliminary Information 2 PROCESSOR Data Sheet Preliminary Information September 1998 IDT WINCHIP 2TM PROCESSOR DATA SHEET This is Version 1.0 of the IDT WinChip 2 Processor data sheet. The latest versions of this data sheet may be obtained from www.winchip.com

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Abstract: 24C01C-I/led 7 segment LDS 5161 AK 12/led 7 segment LDS 5161 AK 24aa32aft-i/lds 7 segment LDS 5161 AK -20/led 7 segment LDS 5161 AH
Contextual Info: intei i486 MICROPROCESSOR • High Performance Design — Frequent Instructions Execute in One Clock — 25 MHz and 33 MHz Clock Frequencies — 80 and 106 Mbyte/Sec Burst Bus — CHMOS IV Process Technology — Dynamic Bus Sizing for 8-, 16- and 32-Bit Busses