INSTRUCTION SET PROCESSOR INTEL Search Results

Contextual Info: intel APPENDIX A INSTRUCTION SET REFERENCE This appendix provides reference information for the instruction set of the family of MCS 96 microcontrollers. It defines the processor status word PSW flags, describes each instruction, shows the relationships between instructions and PSW flags, and shows hexadecimal opcodes,

4AM32

Contextual Info: SMJ320C80 DIGITAL SIGNAL PROCESSOR SG U S 0 2 5 - AUGUST 1998 • Single-Chip Parallel Multiple Instruction/Multiple Data MIMD Digital Signal Processor (DSP) • More Than Two Billion RISC-Equivalent Operations per Second • Master Processor (MP) - 32-Bit Reduced Instruction Set

Contextual Info: i n y , APPENDIX A INSTRUCTION SET REFERENCE This appendix provides reference information for the instruction set of the family of MCS 96 microcontrollers. It defines the processor status word PSW flags, describes each instruction, shows the relationships between instructions and PSW flags, and shows hexadecimal opcodes,

ARM SC100 7816

Abstract: ISO7816-2 AT91SC192192CT-USB ISO7816 ISO7816-3 LQFP64 SC100 6556a ARM SC100 Architecture inter chip usb
Contextual Info: Features General • Based on the ARM SC100 SecureCore™ 32-bit RISC Processor • Two Instruction Sets • • • • • • • • – ARM High-performance 32-bit Instruction Set – Thumb® High-code-density 16-bit Instruction Set Von Neumann Load/Store Architecture

ARM SC100

Abstract: ARM processor securecore ARM processor pin configuration ARM SC100 Architecture ARM SC100 7816 AT91SC512384RCT ISO7816-2 "flash controller" 7816 nand 6525a ISO7816-3
Contextual Info: Features General • Based on the ARM SC100 SecureCore 32-bit RISC Processor • Two Instruction Sets • • • • • • • • – ARM High-performance 32-bit Instruction Set – Thumb® High-code-density 16-bit Instruction Set Von Neumann Load/Store Architecture

ARM SC100

Abstract: ARM processor pin configuration ARM processor based Circuit Diagram ISO7816-2 AT91SC464384RCU ARM SC100 7816 AT91SC512384RCT CRC16 ISO7816-3 SC100
Contextual Info: Features General • Based on the ARM SC100 SecureCore™ 32-bit RISC Processor • Two Instruction Sets • • • • • • • • • – ARM High-performance 32-bit Instruction Set – Thumb® High-code-density 16-bit Instruction Set Von Neumann Load/Store Architecture

EF86

Abstract: NS486SXF CS16 NS486
Contextual Info: Appendix A: Key Processor Differences from the ‘486 Appendix A: Key Processor Differences from the ‘486 The NS486SXF’s 32-bit processor is instruction set compatible with the standard Intel486 processor with the following exceptions: 1 NS486SXF operates in 16-bit and 32-bit protected

Contextual Info: MC9S08JM16 MC9S08JM8 Data Sheet HCS08 Microcontrollers MC9S08JM16 Rev. 2 5/2008 freescale.com MC9S08JM16 Series Features 8-Bit HCS08 Central Processor Unit CPU • • • • • 48 MHz HCS08 CPU (central processor unit) 24 MHz internal bus frequency HC08 instruction set with added BGND instruction

AB32

Abstract: AB34 SM320C80 active aa33
Contextual Info: SM320C80 DIGITAL SIGNAL PROCESSOR SGUS021 – AUGUST 1996 D D D D D D D D D D D D D Single-Chip Parallel Multiple Instruction / Multiple Data MIMD DSP More Than Two Billion RISC-Equivalent Operations per Second Master Processor (MP) – 32-Bit Reduced Instruction Set

C8050

Contextual Info: TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B - JULY 1994 - REVISED OCTOBER 1997 D Single-Chip Parallel Multiple D D D D D D D D D D D Instruction/Multiple Data MIMD DSP More Than Two Billion RISC-Equivalent Operations per Second Master Processor (MP) - 32-Bit Reduced Instruction Set

ic isl 887

Abstract: T85 1e4 Switch TMS320C80 MP 1008 es MIP 289 C8050 AH-34 alu module for 32 bit processor GLC 555 texas instrument
Contextual Info: TMS320C80 DIGITAL SIGNAL PROCESSOR S P R S Q 2 3 A -JULY 1994 - R E VIS ED MARCH 1996 • Single-Chip Parallel Multiple Instruction/Multiple Data MIMD DSP • More Than Two Billion RISC-Equivalent Operations per Second • Master Processor (MP) - 32-Bit Reduced Instruction Set

atmel jtag ice

Abstract: ARM processor based Circuit Diagram 32-bit microcontrollers 3-channel volume controller ARM microcontroller ARM processor pin configuration arm7tdmi Package AT91R40807 4 bit barrel shifter ARM processor data sheet
Contextual Info: Features • Incorporates the ARM7TDMI ARM Thumb® Processor Core • • • • • • • • • • • – High-performance 32-bit RISC Architecture – High-performance 32-bit ARM Instruction Set – High-density 16-bit Instruction Set – Leader in MIPS/Watt

ARM SC100

Abstract: atmel at45db642D AT45DB642D ARM SC100 7816 ARM SC100 Architecture at45DB64 ISO7816-2 AT91SC512384-8M AT91SC512384RCT SC100
Contextual Info: Features General • Based on the ARM SC100TM SecurCoreTM 32-bit RISC Processor • Two Instructions Sets • ARM High-performance 32-bit Instruction Set •Thumb® High-code-density 16-bit Instruction Set • Von Neumann Load/Store Architecture • Single 32-bit Data Bus for Instructions and Data

6553a

Abstract: ATV4-91SC ARM SC100 ARM SC100 7816 AT91SC512384-128M AT91SC512384RCT SC100 "flash controller" 7816 nand securcore
Contextual Info: Features General • Based on the ARM SC100TM SecurCoreTM 32-bit RISC Processor • Two Instructions Sets • ARM High-performance 32-bit Instruction Set •Thumb® High-code-density 16-bit Instruction Set • Von Neumann Load/Store Architecture • Single 32-bit Data Bus for Instructions and Data

80960VH

Abstract: INTEL DX2 80960JT AD10 MA11 cc5r
Contextual Info: i960 VH Embedded-PCI Processor Preliminary Datasheet Product Features • ■ ■ ■ High Performance 80960JT Core — Sustained One Instruction/Clock Execution — 16 Kbyte Two-Way Set-Associative Instruction Cache — 4 Kbyte Direct-Mapped Data Cache

R8051XC2

Abstract: verilog code for baud rate generator verilog code R8051XC2 r8051xc2-b 80515 80517 frequency counter using 8051 verilog code for slave SPI with FPGA verilog code 16 bit UP COUNTER verilog code for uart communication
Contextual Info: Fully compatible with the MCS 51 instruction set R8051XC2 High-Performance, Configurable, 8-bit Microcontroller Core The R8051XC2 configurable processor core implements a range of fast, 8-bit, microcontrollers that execute the MCS®51 instruction set. The IP core runs with a single clock per machine cycle, and requires an average of 2.12

5a6h

Contextual Info: intel CHAPTER 6 INSTRUCTION SET REFERENCE This chapter provides detailed information about each instruction available to the i960 Rx I/O processor. Instructions are listed alphabetically by assembly language mnemonic. Format and notation used in this chapter are defined in section 6.1 . NOTATION pg. 61 .

80960JT

Abstract: 80960VH AD10 MA11 273179
Contextual Info: i960 VH Embedded-PCI Processor Advance Information Datasheet Product Features • ■ ■ ■ High Performance 80960JT Core — Sustained One Instruction/Clock Execution — 16 Kbyte Two-Way Set-Associative Instruction Cache — 4 Kbyte Direct-Mapped Data Cache

80960JT

Abstract: 80960VH AD10 MA11
Contextual Info: i960 VH Embedded-PCI Processor Advance Information Datasheet Product Features • ■ ■ ■ High Performance 80960JT Core — Sustained One Instruction/Clock Execution — 16 Kbyte Two-Way Set-Associative Instruction Cache — 4 Kbyte Direct-Mapped Data Cache

C8050

Abstract: SK14-13
Contextual Info: TMS320C80 DIGITAL SIGNAL PROCESSOR S P R S 0 2 3 A -J U L Y 1994 - R EV IS E D M ARCH 1996 • Single-Chip Parallel Multiple Instruction/Multiple Data MIMD DSP • More Than Two Billion RISC-Equivalent Operations per Second • Master Processor (MP) - 32-Bit Reduced Instruction Set

MB86901

Abstract: MB89251 Fujitsu MB86900 mb86900 MB86902 instruction set Sun SPARC T8 MB86931-20ZF-G
Contextual Info: MB86931 930 Series 32–BIT RISC EMBEDDED PROCESSOR/ INTERRUPT CONTROLLER/TIMER/USART MAY 24, 1994 FEATURES • 40 MHz 25ns/cycle operating frequency • SPARC high performance RISC processor – 2 Kbytes 2–way set associative instruction and data caches.

Intel i960 VH Embedded-PCI Processor Provides Integrated Memory Control and PCI Bus Interface

Contextual Info: i960 VH Embedded-PCI Processor Advance Information Datasheet Product Features • High Performance 80960JT Core — Sustained One Instruction/Clock Execution — 16 Kbyte Two-Way Set-Associative Instruction Cache — 4 Kbyte Direct-M apped Data Cache — Sixteen 32-Bit Global Registers

Contextual Info: irrte l. CHAPTER 6 INSTRUCTION SET REFERENCE This chapter provides detailed information about each instruction available to the i960 Hx processor. Instructions are listed alphabetically by assembly language mnemonic. Format and notation used in this chapter are defined in section 6.1, “NOTATION” pg. 6-1 .

transistor b1240

Abstract: B1240 transistor B1240 r DDR333 PAR64 PC2700 REQ64
Contextual Info: Intel 80333 I/O Processor Datasheet Product Features • ■ ■ ■ ■ ■ ■ Integrated Intel XScale® core — 500, 667 and 800 MHz — ARM* V5TE Compliant — 32 KByte, 32-way Set Associative Instruction Cache with cache locking — 32 KByte, 32-way Set Associative Data