ICT PEEL Search Results

Contextual Info: Preliminary Data INTERNATIONAL CMOS TECHNOLOGY, INC. INTERNATIONAL C M O S 37E D H March 1991 4640707 0D0043T 1 IS ICT PEEL 22CV10A CMOS Programmable Electrically Erasable Logic Device Featu res ^ ^ ^ ~<^~7 Architectural Flexibility — 132 product term x 44 input AND array

22CV10Z

Contextual Info: S4E D 4ÔH0707 000107S 17b • ICT I C T INC , INC. PEEL 22CV10Z "Zero Power" CMOS Programmable Electrically Erasable Logic Device Features ■ Advanced CMOS EEPROM Technology ■ High Performance and Ultra-Low Power — tpD = 25ns, fmax=33.3MHz — Ice = 5mA at 1MHz

Contextual Info: SME D MÖM07D7 GGOlGbb l b 3 • ICT I C T INC 'T tft'tf-V 'J , INC. PEEL 22CV1OA-15/PEEL 22CV1OAL-15 CMOS Programmable Electrically Erasable Logic Device Features Advanced CMOS EEPROM Technology Architectural Flexibility — 132 product term x 44 input AND array

Contextual Info: l ^ = • INC. PEEL 16V8 Data Sheet October 1994 4Ô4G7Q7 00014b5 ^50 ■ [ [U Advanced Designation The "Advanced” designation on an ICT data sheet indicates that the product is not yet ready for release. The specifications are subject to change, are based on design goals or preliminary part evaluation, and

EP600PC

Abstract: gal22v8 GAL22CV10 EP600PC-3 DPLD610-25 EP600DC-3 PPLD610-25 ep600pc-45 EP910PC-40 EP900PC
Contextual Info: PinPin-Compatible PEEL Array Cross Reference Package, speed and power options Altera EP312 EP600PC EP600PC-45 EP600PC-3 EP600DC* EP600DC-3* EP610PC-35 EP610PC-30 EP610PC-25T EP610PC-25 EP610PC-20T EP610PC-20 EP610PC-15T EP610PC-15 EP610PI-30 EP610DC-35*

Contextual Info: September 1994 Preliminary Commercial INC. PEEL 22CV8 -15/-25 CMOS Programmable Electrically Erasable Logic Device Features Low Power Alternative to Standard PLDs — Lower power than quarter-power PALs and GALs — 10mA typical/15mA maximum power CMOS Electrically Erasable Technology

PEEL22V10AZ

Contextual Info: September 1994 Preliminary Commercial INC. TM . PEEL 22V10AZ -15/-25 CMOS Programmable Electrically Erasable Logic Device Features Ultra Low Power — Ice = 25p.A typical at standby — Icc = 3.5mA (typical) at 1MHz — tpD = 15ns and 25ns versions • Architectural Flexibility

Contextual Info: September 1994 Commercial Preliminary INC. PEEL 20V8 -15/-25 CMOS Programmable Electrically Erasable Logic Features Compatible with Popular 20V8 Devices — 20V8 socket and function compatible — Programs with standard 20V8 JEDEC file — 24-pin DIP/SOIC, 28-pin PLCC packages

22CV10AP

Abstract: 22cv10 nte quick cross ict peel 18CV8J palce programmer schematic blackjack vhdl code PA7140J-20 INTEL PLD910 PALCE610
Contextual Info: Data Book General Information PEEL Arrays PEEL Devices Special Products and Services Development Tools Application Notes and Reports Package Information PLACE Users Manual_ Introduction to PLACE PLACE Installation Getting Started with PLACE Operation Reference Guide

Contextual Info: Preliminary Commercial PEEL 22LV10AZ-25 CMOS Programmable Electrically Erasable Logic Device FEATURES • Low Voltage, Ultra Low Power Operation - Vcc = 2.7 to 3.6 V - Icc =25 uA typical at standby - Icc = 2 mA (typical) at 1 MHz - Meets JEDEC LV Interface Spec (JESD8-A)

Contextual Info: INTERNATIONAL C M O S MÔ4D7Q7 00DQ3SÖ 1 37E D Product Preview INTERNATIONAL CMOS TECHNOLOGY, INC. PEEL 20CG10-12/PEEL 20CG10=15 CMOS Programmable Electrically Erasable Logic Device Features • 1 Micron CMOS EEPROM Technology Architectural Flexibility — 92 product temi X 44 input AND array

Contextual Info: INTERNATIONAL C M O S 5SE D 4flMQ707 DOOQMl 2 Product Preview INTERNATIONAL CMOS TECHNOLOGY, INC. 7 PEElIM 20CG10-12/PEE! 20CG1 0-15 CMOS Programmable Electrically Erasable Logic Device Features • 1 Micron CMOS EEPROM Technology Architectural Flexibility

Contextual Info: Preliminary Commercial PEEL 18LV8Z-25 CMOS Programmable Electrically Erasable Logic Device FEATURES • Low Voltage, Ultra Low Power Operation - Vcc = 2.7 to 3.6 V - Icc =25 uA typical at standby - Icc = 2 mA (typical) at 1 MHz - Meets JEDEC LV Interface Spec (JESD8-A)

Contextual Info: Preliminary Commercial IN C . PEEL 22CV1 OAZ -15/-25 CMOS Programmable Electrically Erasable Logic Device Features Architectural Flexibility — 133 product term x 44 input AND array — Up to 22 inputs and 10 I/O pins — 12 possible macrocell configurations

Contextual Info: , INC. PEEL 20CG1 OA-15/PEEL™ 20CG1OAL-15 C M O S Program m able Electrically Erasable Logic Device F e a tu re s • Advanced CMOS EEPROM Technology ■ Architectural Flexibility — 92 product term X 44 input AND array — Up to 22 inputs and 10 outputs

Contextual Info: S4E D 4040707 DDQ1D50 ÖTb « I C T I C T INC , INC._ PEEL 20CG1 OA-15/PEEL™ 20CG1OAL-15 CMOS Programmable Electrically Erasable Logic Device Features T 'M b - i'î 'Ç n • Architectural Rexfciirryr I — 92 product term X 44 input AND array

Contextual Info: 37E D INTERNATIONAL C M O S 4040707 000030b b INTERNATIONAL CMOS TECHNOLOGY, INC. Product Preview T-46-19-07 , TM PEEL 173-15 CMOS Programmable Electrically Erasable Logic Device Features • ADVANCED CMOS EEPROM TECHNOLOGY ■ FPLA ARCHITECTURE — 12 inputs and 10 l/Os

PEEL22CV10P

Abstract: ict PEEL22cv10p
Contextual Info: INTERNATIONAL C M O S 9: 3 7E 4 0 * 4 0 70 7 D 0Q003bb Product Previev; INTERNATIONAL CMOS TECHNOLOGY, INC. T ^ 6 - Í 9 0 / PEELLm 22CV1 0-12/PEE1T22CV10=15 CMOS Programmable Electrically Erasabi Logic Device Features Architectural Flexibility — 132 product term x 44 input AND array

Contextual Info: Preliminary Information INC. PEEL 173-12/PEEL™173-15 CMOS Programmable Electrically Erasable Logic Device Features ADVANCED CMOS EEPROM TECHNOLOGY FPLA ARCHITECTURE — 12 inputs and 10 l/Os — Programmable AND/OR arrays — 42 product terms: 32 logic terms, 10 control terms

Contextual Info: INTERNATIONAL SSE D C M O S 4040707 ODOöni 7 Product Preview INTERNATIONAL CMOS TECHNOLOGY, INC. PEEC"22CV1 0-12/PEEll"22CV10-15 CMOS Programmable Electrically Erasable Logic Device Features Architectural Flexibility — • 132 product term x 44 input AND array

Contextual Info: Preliminary Data INTERNATIONAL CMOS TECHNOLOGY, INC. March 1991 PEEL 22CV10A CMOS Programmable Electrically Erasable Logic Device Features • Advanced CMOS EEPROM Technology Architectural Flexibility — 132 product term x 44 input AND array — Up to 22 inputs and 10 outputs

Contextual Info: Commercial/ Industrial INC. PEEL 22CV10A -5/-7/-10/-15/L-15/-25 CMOS Programmable Electrically Erasable Logic Features High Speed/Low Power — Speeds ranging from 5ns to 25ns — Power as low as 67mA at 25MHz Architectural Flexibility — 132 product term X 44 input AND array

ICT Peel

Abstract: International CMOS Technology 82s173 PEEL22CP210 PLS173 PEEL programming
Contextual Info: INTERNATIONAlr-CMO! TECHNOLOGY INC. Product Preview nrrrmhor 11ftfi I \PEEL2 CMOS Programmable Electrically Erâsabfèf1Logic Device O S £/> Ky Features • ADVANCED CMOS E2PROM TECHNOLOGY — Super-sets the Signetics PLS173 _~ — PC-based software translates existing JEDEC files to

Contextual Info: Product Preview INTERNATIONAlr-CMOi TECHNOLOGY INC. Ftrrrmhnrlinii I \PEEL2 CMOS Programmable Electrically EràsàtrtèT Logic Device: Features ADVANCED CMOS E2PROM TECHNOLOGY — CMOS: 25mA + .7mA/MHz Max — TTL: 35mA + .7mA/MHz Max HIGH PERFORMANCE —