IC TTL AND NOT XOR NOR XNOR OR Search Results

Verilog code of 1-bit full subtractor

Abstract: Verilog code "1-bit full subtractor" verilog hdl code for D Flip flop accumulator verilog code for jk flip flop vhdl code for barrel shifter verilog code for 64 bit barrel shifter XOR Gates 5D208 8 BIT ALU design with verilog code full adder using x-OR and NAND gate
Contextual Info: Full Custom Design Expertise • • • • • • • • • • Microcontroller DSP PC peripheral Remote controller Telephone Communications Speech synthesizer Melody/Rhythm Home appliances Hand-held LCD games Process Process Operating Voltage 7.0µm TOCMOS

ic configuration of xnor gates

Abstract: SY55851 SY55851A SY55851AKI SY55851AKITR SY55851KITR 851A ic ttl and not xor nor xnor or K101 marking code
Contextual Info: 2.5V/3V, 3.0GHz CML AnyGate ANY LOGIC w/50Ω or 100Ω OUTPUTS SuperLite™ SY55851 SY55851A DESCRIPTION FEATURES • Guaranteed AC parameters over temperature: • fMAX > 3.0GHz SY55851A • tr / tf < 100ps • Propagation delay < 280ps ■ Guaranteed operation over –40°C to +85°C

Contextual Info: DS1012 DS1012 2-in-1 Sub-Miniature Silicon Delay Line with Logic DALLAS SEMICONDUCTOR FEATURES PIN ASSIGNMENT • All-silicon time delay • 53 jiW max. CMOS quiescent mode • Surface mount 8-pin mini-SOIC and standard 8-pin DIP 1N1 £ 1 O UT3C 2 OUT1 Q 3

851A

Abstract: marking 851A
Contextual Info: 2.5V/3V, 3.0GHz CML AnyGate ANY LOGIC w/50Ω or 100Ω OUTPUTS SuperLite™ SY55851 SY55851A DESCRIPTION FEATURES • Guaranteed AC parameters over temperature: • fMAX > 3.0GHz SY55851A • tr / tf < 100ps • Propagation delay < 280ps ■ Guaranteed operation over –40°C to +85°C

IC AND GATE 7408 specification sheet

Abstract: 74LS183 74LS96 SN 74168 7486 XOR GATE IC 74LS192 IC 7402, 7404, 7408, 7432, 7400 IC 7486 for XOR gate IC 74183 74LS193 function table
Contextual Info: PLS-EDIF Bidirectional EDIF Netlist Interface to MAX+PLUS Software Data Sheet September 1991, ver. 3 Features u J Provides a bidirectional netlist interface b etw ee n M A X + P L U S and other m ajor C A E softw are packages Sup ports the industry-standard Electronic Design Interchange Format

sn 74373

Abstract: SN 74114 logic diagram of ic 74112 IC 7486 xor IC 7402, 7404, 7408, 7432, 7400 7486 xor IC sn 74377 IC TTL 7486 xor IC TTL 7495 diagram and truth table IC 74374
Contextual Info: PLS-WS/SN MAX+PLUS II Programmable Logic Software for Sun Workstations Data Sheet September 1991, ver. 1 Features J J □ □ □ J □ IJ Softw are supp ort for Classic, M A X 5000, M A X 7000, and S T G EPLD s Runs on Sun S P A R C s ta tio n s with S u n O S version 4.1.1 or h igher

ic ttl and not xor nor xnor or

Abstract: K101 marking code xnor ttl marking 851A
Contextual Info: SuperLite SY55851 SY55851A FINAL 2.5V/3V, 3.0GHz CML AnyGate™ANY LOGIC w/50Ω or 100Ω OUTPUTS DESCRIPTION FEATURES • Guaranteed AC parameters over temperature: • fMAX > 3.0GHz SY55851A • tr / tf < 100ps • Propagation delay < 280ps ■ Guaranteed operation over –40°C to +85°C

SY55851

Abstract: SY55851A SY55851AUKG SY55851AUKI SY55851AUKITR SY55851UKG SY55851UKGTR SY55851UKI SY55851UKITR 851A
Contextual Info: Micrel, Inc. SuperLite SY55851 SuperLite™ SY55851A ANYGATE 2.5V/3V, 3.0GHz ANY LOGIC SY55851 DEVICE WITH 50Ω or 100Ω CML OUTPUTS SY55851A FEATURES • Guaranteed AC parameters over temperature: • fMAX > 3.0GHz SY55851A • tr / tf < 100ps • Propagation delay < 280ps

Contextual Info: 16-BIT CMOS ERROR DETECTION AND CORRECTION UNIT Integrated Device Technology, Inc. IDT39C60 IDT39C60-1 IDT39C60A IDT39C60B FEATURES: DESCRIPTION: • • The IDT39C60 family are high-speed, low-power, 16-bit Error Detection and Correction Units which generate checkbits on a 16-bit data field according to a m odified Hamming

lm324 dc to ac inverters diagram

Abstract: IGC20000
Contextual Info: G E CO-. CUSTOM I N T E G R A T E » 50 D ë 30740=15 0 0 0 0 0 0 1 fi 58C 000Ò1 3 8 7 4 0 9 5 G E CO» CUSTOM INTEGRATED /" " T -42-11-09 & iß ¿ ¡r The IGC20000 Series CMOS Gate Arrays A? — Facilitates conversion of 7400 and 4000based designs —Complete macro library of TTL or CMOS

Contextual Info: w W 16-BIT CM O S ERROR DETECTION AND CO RRECTIO N UNIT IDT39C60A IDT ^ C6/2“ 1 IDT39C60 Inte3 rated Device Technology. Inc. MICROSLICE PRODUCT FEATURES: DESCRIPTION: • The IDT39C60 fam ily are high-speed, low-power, 16-bit Error De­ tection and Correction Units which generate check bits on a 16-bit

Contextual Info: IME D INTEGRATED DEVICE • 4Ö2S771 0003^22 1 ■ 16-BIT CMOS ERROR DETECTION AND CORRECTION UNIT MICROSLICE PRODUCT FEATURES: • • ■ T -¥ £ -/7 Pin-compatible to all versions of the 2960 • Military product available compliant to MIL-STD-883, Class B

MAX2852

Abstract: AM2960
Contextual Info: Am2960/Am2960-1 /Am2960A Advanced Micro Devices Cascadable 16-Bit Error Detection and Correction Unit DISTINCTIVE CHARACTERISTICS Boosts Memory Reliability Corrects all single-bit errors. Detects all double and some triple-bit errors. Very High Speed Perfect or MOS microprocessor, minicomputer, and

Dallas 1012 D4

Contextual Info: D S 1012 DS1012 DALLAS SEMICONDUCTOR FEATURES 2-in-1 Sub-M iniature Silicon Delay Line with Logic PIN ASSIGNMENT • All-silicon time delay IN1 • 53 |uW max. CMOS quiescent m ode OUT3 E 1 E 2 OUT1 □ • Surface mount 8-pin m ini-SO IC and standard 8-pin

mx41 plc

Abstract: 2-BIT Full-Adder CP20K NEC lcd inverter schematic NEC CP20K FPGA nec cmos CLS199 LDPC Decoder vhdl RAM64X4 9020 8pin
Contextual Info: MAR i o 1983 C P20K 0 .8 -M IC R O N fp g a s NEC Electronics Inc. February 1993 Description Figure 1. CP20K FPGAs NEC Electronics Inc. and Crosspoint Solutions, Inc. have joined forces to offer to system designers an expedient way to prototype in Field Program m able Gate Arrays

dmo 365 rn

Abstract: AM2960DC T-55 SOCO
Contextual Info: Am2960/Am2960A 16-Bit Error Detection and Correction Unit ADVANCED INFORMATION DISTINCTIVE CHARACTERISTICS Boosts Memory Reliability Corrects all single-bit errors. Detects all double and some triple-bit errors. Reliability of dynamic RAM systems is increased more than 60-fold.

Contextual Info: NECES001 C P20K 0 .8 -M IC R O N NEC Electronics Inc. fpgas February 1993 Description Figure 1. CP20K FPGAs NEC Electronics Inc. and Crosspoint Solutions, Inc. have joined forces to offer to system designers an expedient way to prototype in Field Programmable Gate Arrays

Contextual Info: 16-BIT CMOS ERROR DETECTION AND CORRECTION UNIT FEATURES IDT39C60 IDT39C60-1 IDT39C60A IDT39C60B • Standard Military Drawing #5962-88613 available for this function • Low-power CEMOS — Military: 100mA max. — Commercial: 85mA (max.) • Fast — Da1a in to Error Delect

dmo 365 rn

Abstract: Am2960 applications note AM2960 AM2960-1 AM2960A pg2s edc 16 cp
Contextual Info: Am2960/Am2960-1 /Am2960A Advanced Micro Devices Cascadable 16-Bit Error Detection and Correction Unit DISTINCTIVE CHARACTERISTICS B oosts M em ory Reliability C orrects all single-bit errors. D etects all double and som e trip le -b it errors. Very High Speed

IDT39C60

Abstract: 39c60
Contextual Info: 16-BIT CMOS ERROR DETECTION AND CORRECTION UNIT IDT39C60 IDT39C60-1 IDT39C60A IDT39C60B FEATURES: DESCRIPTION: • • T h e ID T 3 9C 60 fa m ily are h igh -spe ed, lo w -p ow er, 16-bit E rror D ete ction and C o rre ctio n U nits w h ic h g e n e ra te che ckbits on a 16-bit d a ta fie ld a cco rd in g to a m o d ifie d H am m ing

Contextual Info: — > 1 ! i Features Product Summary fcM Figure 1 • Partial View o f an ACT 1 Device A C T 1 D e v ic e S tru c tu re A partial view of an ACT 1 device Figure 1 depicts four logic modules and distributed horizontal and vertical Interconnect tracks. PLICE antifuses, located at intersections of the

Contextual Info: ACT 1 and A C T 2 Military Field P rogram m able G ate Arrays ACT 1 Features ACT 2 Features • Up to 2000 Gate Array Gates 6000 PLD/LCA™ equivalent gates • Replaces up to 53 TTL Packages • Replaces up to 17 20-Pin PAL Packages • Design Library with over 250 Macros

Contextual Info: irrte l. CHAPTER 6 INSTRUCTION SET REFERENCE This chapter provides detailed information about each instruction available to the i960 Hx processor. Instructions are listed alphabetically by assembly language mnemonic. Format and notation used in this chapter are defined in section 6.1, “NOTATION” pg. 6-1 .

10 GHz wideband mixer

Abstract: HMC676LP3E
Contextual Info: g ra tin Ye ar s 25 Ce leb  Inn ov ce vi y lit  ion Qua at Product Selection Guide Analog, Digital & Mixed -Signal ICs, Modules, Subsystems & Instrumentation, DC - 110 GHz Automotive Telematics & Sensors Broadband Cable Modem, CATV, DBS & VoIP WiMAX, WiBro, WLAN & UWB