IC LOGIC GATES Search Results

Contextual Info: STP2024 S un M ic r o e l e c t r o n ic s J u ly 1997 APC System Logic Chip DATA SHEET D e s c r ip t io n The STP2024 System Logic Chip provides additional features for SBus based systems. It has two m ajor logic blocks: an audio DM A controller and a glue logic block. The DM A controller consum es the bulk of the logic,

14081b

Abstract: 4584b equivalent
Contextual Info: General-purpose CMOS Logic IC Series BU4S,BU4000B Series High Voltage CMOS Logic ICs <Logic Gate> BU4001B/F,BU4011B/F/FV,BU4030B/F,BU4070B/F, No.11050EBT03 ●Description BU4001B series ICs are 2-input positive logic NOR gates, each with four built-in circuits. A buffer achieved by an inverter

BU4000B

Abstract: 4584BE 4584b equivalent 4584B BU4001B BU4081F 4069UB 4093B SOP14 package tray
Contextual Info: General-purpose CMOS Logic IC Series BU4S,BU4000B Series High Voltage CMOS Logic ICs <Logic Gate> BU4001B/F,BU4011B/F/FV,BU4030B/F,BU4070B/F, No.09050EAT03 ●Description BU4001B series ICs are 2-input positive logic NOR gates, each with four built-in circuits. A buffer achieved by an inverter

dtl logic gates

Abstract: ttl NAND gate circuit series inverter circuit diagrams 9000 ttl 930 series dtl ttl NAND gate with expander K 9008 TTL 7430 6 a 8 mic 4 pin mic circuit
Contextual Info: Logic Integrateci Circuits, MIC 9 0 0 0 Series TTL C irc u it F unctions Compatible w ith M IC 930 Series DTL and other TTL and DTL Series M IC M IC M IC M IC M IC M IC M IC M IC M IC M IC M IC M IC M IC 9000 9001 9002 9003 9004 9005 9006 9007 9008 9009 9012

IC of XNOR GATE

Abstract: IC of XOR GATE AND8408 AND8408/D ULLGA8 Package create pulse XOR schmitt trigger ic xnor frequency doubler comparator using 2 xor gates
Contextual Info: AND8408/D Pulse Generation and Signal Conditioning Circuits Using Configurable Multifunction Logic Gates http://onsemi.com Prepared by: Jim Lepkowski ON Semiconductor APPLICATION NOTE Introduction A configurable multifunction logic gate is a versatile IC that can be used to create pulse generation and signal

ELM7SxxB

Abstract: ELM7S14B ELM7S04B ELM7S02 ELM7S08 ELM7S00 ELM7S04 ELM7S86 74HC ELM7S00B
Contextual Info: ELM7Sxx,ELM7SxxB SERIES CMOS LOGIC IC • GENERAL DESCRIPTION ・ELM7Sxx,ELM7SxxB Series are CMOS ICs. They realize a high speed operation similar to LS-TTL with a lower power consumption by CMOS features. An inner circuit structure of 3-stages logic gates obtains wider

N8815

Abstract: 8815 N8885 N8875 S8815 8815A 8885A S8885 S8875 8875A
Contextual Info: S IG N E T IC S DCL 8815 DUAL 4-INPUT NOR GATE 8875 TRIPLE 3-INPUT NOR GATE 8885 QUAD 2-INPUT NOR GATE NTiGBATte» CIRCUITS BASIC C IR C U IT SCHEMATIC The 8815, 8875 and 8885 gates p e r f o r m the logic NOR function for p ositive logic the logic "ONE" is

930 dtl

Abstract: dtl 946 ic 930 series dtl 946-5D 951 monostable MIC 951 monostable MIC945 936 dtl a 933 transistor dtl 932
Contextual Info: Logic Integrated Circuits, MIC 9 3 0 Series DTL Circuit Functions M IC M IC M IC M IC M IC M IC M IC M IC M IC M IC M IC M IC M IC M IC M IC M IC M IC MIC 930 932 933 936 937 944 945 946 948 949 950 951 961 963 1890 = M IC 9093 1896 = M IC 9094 9097 9099 Dual 4-input NAND gate with fan-in expander nodes

DM7425N

Contextual Info: National mSASemiconductor 5425/DM7425 Dual 4-Input NOR Gate with Strobe General Description This device contains two, 4-input gates that perform the log­ ic NOR function. The output of each NOR gate is gated (strobed) by pin 3 and pin 11 by positive true logic i.e., logic

Contextual Info: LAT T IC E S E M I C O N D U C T O R □flE D Lattice 330^^ pLSl and ispLSI" 1032 High-Density Programmable Logic Functional Block Diagram Features • PROGRAMMABLE AND IN-SYSTEM PROGRAMMABLE HIGH DENSITY LOGIC — High Speed Global Interconnect — 6000 PLD Gates

DM7425N

Abstract: 5425DMQB 5425FMQB DM74 DM7425 DM7425J J14A N14A W14B 2 input nor gate 24v
Contextual Info: National ÆüA Semiconductor 5425/DM7425 Dual 4-input NOR Gate with Strobe General Description This device contains two, 4-input gates that perform the log­ ic NOR function. The output of each NOR gate is gated (strobed) by pin 3 and pin 11 by positive true logic i.e., logic

truth table inverter gate 74

Abstract: 74HC74
Contextual Info: 6. HOW TO R E A D MI L T Y PE LOGIC S Y M B O LS A ND TRUTH TA B L ES 6 -1 H o w to read M I L typo L o g ic S y m b o l* Tkble 6-1 shows the MIL type logic symbols used in high-speed CMOS IC This logical chart is based on M1L-STD-806B. Clocked inverters and transmission gates employ specific symbols.

0002B16

Contextual Info: LAT T IC E S E M I C O N D U C T O R bflE D Lattice High-Density Programmable Logic Functional Block Diagram • PROGRAMMABLE AND IN-SYSTEM PROGRAMMABLE HIGH DENSITY LOGIC — High-Speed Global Interconnect — 2000 PLD Gates — 32 I/O Pins, Four Dedicated Inputs

Contextual Info: June 1997 FAIRCHILD M IC O N D U C T O R m FDC633N N-Channel Logic Level Enhancement Mode Field Effect Transistor General Description Features These N-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary,

NDS351N

Contextual Info: FAIRCHILD SEM IC ONDUCTO R March 1996 tm NDS351N N-Channel Logic Level Enhancement Mode Field Effect Transistor General Description Features These N-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, D M O S technology. This

fds6930

Contextual Info: F/\IRCHII_0 M IC D N D U C T O R July 1998 tm FDS6930A Dual N-Channel, Logic Level, PowerTrench MOSFET G eneral D escription Features These N-Channel Logic Level MOSFETs are produced using Fairchild Sem iconductor's advanced PowerTrench process that has been

P6030L

Abstract: 52A zener
Contextual Info: g ^ IR Ç H I^ M IC D N D U C T Q R June1996 tm NDP6030L / NDB6030L N-Channel Logic Level Enhancement Mode Field Effect Transistor Features General Description These N-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's

Diode lt 725

Abstract: P6020P
Contextual Info: Sept mber 1997 s e m ic d n d u c t o r NDP6020P / NDB6020P P-Channel Logic Level Enhancement Mode Field Effect Transistor General Description Features These logic level P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary,

Contextual Info: FAIRCHILD S E M IC O N D U C T O R June 1997 tm NDP6030PL / NDB6030PL P-Channel Logic Level Enhancement Mode Field Effect Transistor General Description Features These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary,

Contextual Info: F A IR C H IL D SEM IC ONDUCTO R A P ril 1998 tm FDP603AL / FDB603AL N-Channel Logic Level Enhancement Mode Field Effect Transistor General Description Features These N-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary,

SOT-23 w02

Abstract: W02 SOT23 W02 sot 23 W02 sot-23 W02 sot t 5.5 w
Contextual Info: April 1999 PAIRÇHILD S E M IC O N D U C T O R tm FDN359AN N-Channel Logic Level PowerTrench MOSFET General Description Features This N-Channel Logic Level MOSFET is produced using Fairchild Semiconductor’s advanced PowerTrench process that has been especially tailored

ir 636P

Abstract: sot333 fdc636p
Contextual Info: f = /\IR G H IL .D May 1998 SEM IC O N D U C T O R i FDC636P P-Channel Logic Level Enhancement Mode Field Effect Transistor General Description Features These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild’s

FDS6912A

Contextual Info: P /\IR C H II_ D M IC D N D U C T Q June 1998 R tm FDS6912A Dual N-Channel, Logic Level, PowerTrench MOSFET General Description Features These N-Channel Logic Level MOSFETs are produced using Fairchild Sem iconductor's advanced PowerTrench process that has been

Contextual Info: July 1998 F/\IRCHII_0 M IC D N D U C T O R i FDS6612A Single N-Channel, Logic Level, PowerTrench MOSFET General Description Features This N-Channel Logic Level MOSFET is produced using Fairchild Semiconductor's advanced PowerTrench process that has been especially tailored to minimize the