I2S SLAVE Search Results

I2S SLAVE Result Highlights (5)

Part	Manufacturer	Description
CD4027BM96E4	Texas Instruments	CMOS Dual J-K Master-Slave Flip-Flop 16-SOIC -55 to 125
CD4027BE	Texas Instruments	CMOS Dual J-K Master-Slave Flip-Flop 16-PDIP -55 to 125
CD4027BF	Texas Instruments	CMOS Dual J-K Master-Slave Flip-Flop 16-CDIP -55 to 125
CD4027BMT	Texas Instruments	CMOS Dual J-K Master-Slave Flip-Flop 16-SOIC -55 to 125
CD4027BEE4	Texas Instruments	CMOS Dual J-K Master-Slave Flip-Flop 16-PDIP -55 to 125

I2S SLAVE Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
AD62550A Abstract: AD8256A TTL buffer signal schmitt trigger Contextual Info: ESMT AD62550A Class-D Audio Power Amplifier with USB / I2S Interface Features z Compliant with USB Specification v1.1, and USB 2.0 full speed z Embedded high efficiency, high performance class D stereo amplifier z Support I2S input and I2S output interface of	Original	ad62550a 48khz me//2000/xp ad8256a +2ttl buffer signal schmitt trigger	PDF
TXM RX 28 Receiver Abstract: TXM RX 23 Receiver IA6 l syncomm IA6 synic SYNIC-IA6002 syncomm SYNIC-IA6 SYNIC IA6002 TXM, Receiver, 16 Pin Configuration Contextual Info: Your Value-added Designer Data Sheet SYNIC – IA6002 Interface Between I2S Data Format and IA6 Transceiver March 11, 2003 Data Sheet Interface Between I2S Data Format and IA6 Transceiver SYNIC-IA6002 1. Block Diagram: RF / I2S Audio Codec / / IA6 Frame Sync	Original	ia6002 synic-ia6002 txm rx 28 receiver txm rx 23 receiver +7ia6 l syncomm ia6 synic syncomm synic-ia6 synic ia6002 txm, receiver, 16 pin configuration	PDF
Contextual Info: ESMT Preliminary AD62550A Class-D Audio Power Amplifier with USB/I2S Interface Features z Compliant with USB Specification v1.1, and USB 2.0 full speed z Embedded high efficiency, high performance class D stereo amplifier z Support I2S input and I2S output interface of	Original	ad62550a me//2000/xp	PDF
AD62550A Contextual Info: ESMT AD62550A Class-D Audio Power Amplifier with USB / I2S Interface Features z Compliant with USB Specification v1.1, and USB 2.0 full speed z Embedded high efficiency, high performance class D stereo amplifier z Support I2S input and I2S output interface of	Original	ad62550a me//2000/xp	PDF
Contextual Info: ESMT AD6255A Class-D Audio Power Amplifier with USB / I2S Interface and Recording function Features z Compliant with USB Specification v1.1, and USB 2.0 full speed z Embedded high efficiency, high performance class D stereo amplifier z Support I2S input and I2S output interface of	Original	ad6255a me//2000/xp	PDF
bead filter Abstract: amplifier with port USB diagram Contextual Info: ESMT AD6255A Class-D Audio Power Amplifier with USB / I2S Interface and Recording function Features z Compliant with USB Specification v1.1, and USB 2.0 full speed z Embedded high efficiency, high performance class D stereo amplifier z Support I2S input and I2S output interface of	Original	48khz me//2000/xp ad6255an ad6255a +2bead filter amplifier with port usb diagram	PDF
AD6255A Abstract: usb amplifier with button control diagram AD8356A ttl buffer TTL Schmitt-Trigger schmitt trigger 1M volume resistor Contextual Info: ESMT AD6255A Class-D Audio Power Amplifier with USB / I2S Interface and Recording function Features z Compliant with USB Specification v1.1, and USB 2.0 full speed z Embedded high efficiency, high performance class D stereo amplifier z Support I2S input and I2S output interface of	Original	ad6255a 48khz me//2000/xp usb amplifier with button control diagram +5ad8356a ttl buffer ttl schmitt-trigger schmitt trigger 1m volume resistor	PDF
Contextual Info: ESMT Preliminary AD6255A Class-D Audio Power Amplifier with USB/I2S Interface and Recording function Features z Compliant with USB Specification v1.1, and USB 2.0 full speed z Embedded high efficiency, high performance class D stereo amplifier z Support I2S input and I2S output interface of	Original	ad6255a me//2000/xp	PDF
i2s philips Abstract: block diagram for asynchronous FIFO testbench of a transmitter in verilog verilog i2s philips I2S bus specification synchronous fifo design in verilog verilog i2s bus Philips Compact Disc Designer Guide Contextual Info:  Meets Philips Inter-IC Sound Bus Specification  Supported modes I2S-APB Inter-IC Sound Bus Megafunction for AMBA APB − I2S Philips − Left Justified − Right Justified − DSP  Two clock domains − APB the host side clock do- main − system clock for the I2S	Original	i2s philips block diagram for asynchronous fifo testbench of a transmitter in verilog verilog i2s +4philips i2s bus specification synchronous fifo design in verilog verilog i2s bus philips compact disc designer guide	PDF
verilog code for amba apb master Abstract: verilog code for apb verilog code for amba apb bus i2s philips synchronous fifo design in verilog verilog code for i2s bus testbench of a transmitter in verilog philips I2S bus specification verilog code for 8 bit fifo register testbench verilog ram asynchronous Contextual Info: Meets Philips Inter-IC Sound Bus Specification Supported modes I2S-APB − I2S Philips Inter-IC Sound Bus Core for AMBA APB − Right Justified − Left Justified − DSP Two clock domains − APB the host side clock do- The I2S-APB core integrates eight channels of Inter-IC Sound compatible serial buses.	Original	verilog code for amba apb master verilog code for apb verilog code for amba apb bus i2s philips +6synchronous fifo design in verilog verilog code for i2s bus testbench of a transmitter in verilog philips i2s bus specification verilog code for 8 bit fifo register testbench verilog ram asynchronous	PDF
ad2410 Contextual Info: Automotive Audio Bus A2B Transceiver AD2410W A2B BUS FEATURES GENERAL DESCRIPTION Line topology Single master, multiple slave Up to 10 meters between nodes Up to 40 meters overall cable length Communication over distance Synchronous data Multichannel I2S/TDM to I2S/TDM	Original	ad2410w d12780f-0-12/14 ad2410	PDF
I2S bus specification Abstract: verilog code for amba apb master verilog code for apb testbench of a transmitter in verilog philips I2S bus specification i2s specification verilog code for amba apb bus testbench verilog ram asynchronous verilog code for digital clock AMBA BUS vhdl code Contextual Info:  Meets Philips Inter-IC Sound Bus Specification  Supported modes I2S-APB  I2S Philips Inter-IC Sound Bus Core for AMBA APB  Right Justified  Left Justified  DSP  Two clock domains  APB the host side clock do- The I2S-APB core integrates eight channels of Inter-IC Sound compatible serial buses.	Original	i2s bus specification verilog code for amba apb master verilog code for apb testbench of a transmitter in verilog +6philips i2s bus specification i2s specification verilog code for amba apb bus testbench verilog ram asynchronous verilog code for digital clock amba bus vhdl code	PDF
verilog code for amba ahb bus Abstract: verilog code AMBA AHB verilog code for amba ahb master ahb slave verilog code verilog code for i2s bus ahb wrapper verilog code verilog code for ahb bus slave ahb slave RTL verilog i2s amba ahb verilog code Contextual Info: I2S core meets the Philips InterIC Sound bus specification Supports Master/Slave and Receiver/Transmitter modes I2S-AHB Eight configurable stereo channels Inter-IC Sound Bus Core for AMBA AHB Data mode capabilities: 22.05, 24; 32, 44.1; 48; 88.2; 96; 176.4; 192kHz	Original	192khz verilog code for amba ahb bus verilog code amba ahb verilog code for amba ahb master +7ahb slave verilog code verilog code for i2s bus ahb wrapper verilog code verilog code for ahb bus slave ahb slave rtl verilog i2s amba ahb verilog code	PDF
Contextual Info: Stereo PDM-to-I2S or TDM Conversion IC ADAU7002 Data Sheet FEATURES GENERAL DESCRIPTION 64x decimation of a stereo pulse density modulation PDM bit stream to pulse code modulation (PCM) audio data Slave I2S or time division multiplexed (TDM) output interface	Original	adau7002 adau7002acbz-r7 adau7002acbz-rl eval-adau7002z +21-21-2012-a d11265-0-7/13	PDF

128fs Contextual Info: LM49450 LM49450 I2S Input, 2.5W/Channel, Low EMI, Stereo, Class D Audio Sub-System withGround Referenced Headphone Amplifier, 3D Enhancement, and Headphone Sense Literature Number: SNAS440C August 4, 2011 I2S Input, 2.5W/Channel, Low EMI, Stereo, Class D Audio	Original	lm49450 snas440c 24-bit 128fs	PDF
CX20745 Abstract: ec16b Contextual Info: CX20745 Low-Power I2S CODEC Data Sheet General Description Features The CX20745 is an Integrated Interchip Sound I2S audio Coder-Decoder (CODEC), with integrated stereo class-D speaker amplifiers and capless headphones with performance that exceeds 100dB Signal-to-Noise Ratio	Original	cx20745 100db 008dsr00 ec16b	PDF
I2S bus specification Abstract: I2S serial bus protocol i2s specification atmel errata sheet at91rm9200 i2s RECEIVER AT91RM92000 AT91RM9200 TSC2301 atmel errata at91rm9200 Contextual Info: Connecting the Atmel ARM-based Serial Synchronous Controller SSC to an I2S-compatible Serial Bus Introduction This Application Note describes the configuration required to connect the Atmel ARMbased Synchronous Serial Controller (SSC) to a device with an I2S-compatible serial	Original	at91rm9200 i2s bus specification i2s serial bus protocol i2s specification +5atmel errata sheet at91rm9200 i2s receiver at91rm92000 tsc2301 atmel errata at91rm9200	PDF
LM492 Abstract: 5 pin PCB Mounted 3.5mm Stereo jack Contextual Info: LM4921 LM4921 Low Voltage I2S 16-Bit Stereo DAC with Stereo Headphone Power Amplifiersand Volume Control Literature Number: SNAS178D LM4921 Low Voltage I2S 16-Bit Stereo DAC with Stereo Headphone Power Amplifiers and Volume Control General Description Key Specifications	Original	lm4921 16-bit snas178d lm492 +15 pin pcb mounted 3.5mm stereo jack	PDF
3.3v regulator Abstract: 3,3v regulator ttl buffer AD62551A schmitt trigger ad8256a Contextual Info: ESMT AD62551A USB controller with external Amplifier and Recording function Features z Compliant with USB Specification v1.1, and USB 2.0 full speed z Support I2S input and I2S output interface of master mode Sampling frequencies Fs ：48kHz z Support recording function	Original	ad62551a 48khz me//2000/xp 32-pin +53.3v regulator 3,3v regulator ttl buffer schmitt trigger ad8256a	PDF
I2S bridge Abstract: AN2682 EPM3064 spi to i2s I2S serial bus protocol vhdl code for spi controller implementation on MAX3000A PWM code using vhdl STM32 TIM1 DMA STR711 Contextual Info: AN2682 Application note Connecting I2S audio devices to the STR7/STR9 MCU Introduction This application note describes how to interface the STR7xx SPI peripheral with an audio device Codec, ADC, DAC, filter. using the I2S protocol via an external interface consisting	Original	an2682 str91x i2s bridge epm3064 +7spi to i2s i2s serial bus protocol vhdl code for spi controller implementation on max3000a pwm code using vhdl stm32 tim1 dma str711	PDF
FLI30602H-AC Abstract: Power Sub Woofer Amplifier spdif input 5.1 woofer dual sub woofer circuit diagram make ypbpr Faroudja FLI30502-AC JESD97 fli30602h Contextual Info: FLI30x02 Single-chip analog TV processor Data Brief Features • Advanced audio enhancement ■ Digital audio support ■ I2S, SPDIF input ■ I2S, SPDIF output ■ Loud speaker, sub woofer, and headphone ■ Analog line in, microphone in, and line out ■	Original	fli30x02 10-bit fli30602h fli30502 +9fli30602h-ac power sub woofer amplifier spdif input 5.1 woofer dual sub woofer circuit diagram make ypbpr faroudja fli30502-ac jesd97	PDF
Contextual Info: ESMT AD62551A USB controller with external Amplifier and Recording function Features z Compliant with USB Specification v1.1, and USB 2.0 full speed z Support I2S input and I2S output interface of master mode z Support recording function z Supports Win Me//2000/XP and MacOS	Original	ad62551a me//2000/xp 32-pin	PDF
Contextual Info: Omnidirectional Microphone with Bottom Port and I2S Digital Output ADMP441 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM I2S SERIAL PORT HARDWARE CONTROL SCK SD WS 09568-001 L/R CHIPEN GND GND VDD POWER MANAGEMENT FILTER TE Figure 1. BOTTOM TOP 09568-015 Teleconferencing systems	Original	admp441 24-bit d09568-0-10/12	PDF
CX20709-21Z Abstract: intercom phone system block diagram CX20709 CX20709-12Z 76-QFN audio USB DAC 24bit three way intercom CX20709-EVK2 echo cancellation audio adc audio i2s 8 channel controller Contextual Info: CX20709 USB/I2S Audio CODEC, Audio/Voice DSP, Stereo Class-D, Headphone Driver Overview The CX20709 is one of Conexant's Audio/ Voice DSP CODEC family solutions with highly integrated hardware DSP, CODEC, Class-D amplifier, USB, I2S, S/PDIF, and I2C interfaces. The solution features a suite	Original	cx20709 cx20709-21z intercom phone system block diagram cx20709-12z +676-qfn audio usb dac 24bit three way intercom cx20709-evk2 echo cancellation audio adc audio i2s 8 channel controller	PDF

I2S SLAVE Search Results

I2S SLAVE Result Highlights (5)

I2S SLAVE Datasheets Context Search

AD62550A

TXM RX 28 Receiver

AD62550A

bead filter

AD6255A

i2s philips

verilog code for amba apb master

ad2410

I2S bus specification

verilog code for amba ahb bus

128fs

CX20745

I2S bus specification

LM492

3.3v regulator

I2S bridge

FLI30602H-AC

CX20709-21Z