HISTORY OF AUTOMATIC PHASE SELECTOR CIRCUIT DIG Search Results

Contextual Info: STC5429 Synchronous Clock for SETS DATASHEET Description Features The RoHS compliant STC5429 is a single chip clock synchronization solution for applications in SDH/SETS, SONET, and Synchronous Ethernet network elements. The device is fully compliant with ITU-T G.813 option 1 and 2,

Contextual Info: STC5455 Synchronous Clock for SETS Data sheet Description Features The RoHS 6/6 compliant STC5455 is a single chip clock synchronization solution for applications in SDH/SETS, SONET, and Synchronous Ethernet network elements. The device is fully compliant with ITU-T G.813 option 1 and 2,

history of automatic phase selector

Abstract: space qualified synthesizer
Contextual Info: STC5420 Synchronous Clock for SETS Data sheet Description Features The RoHS 6/6 compliant STC5420 is a single chip clock synchronization solution for applications in SDH/SETS, SONET, and Synchronous Ethernet network elements. The device is fully compliant with ITU-T G.813 option 1 and 2,

history of automatic phase selector

Abstract: R2598 ami c21 GR O11 213E ACS8510 AM27C64 EZ1086 R102 block diagram of moving message display using 805
Contextual Info: EVALUATION BOARD ACS8510 V2-EVB Advanced Communications SETS - Synchronous Equipment Timing Source Revision 2.04 March 2001 DESCRIPTION FEATURES The ACS8510 V2-EVB is an evaluation kit for exercising and evaluating the functions of the ACS8510 V2 SETS Synchronous Equipment Timing Source SDH and

Contextual Info: STA5620A STA5620C Fully integrated RF front-end receiver for GPS applications Features • Low IF architecture fIF = 4fO ■ Minimum external components ■ VGA gain internally regulated ■ On chip programmable PLL ■ Typ. 2.7 V supply voltage ■ SPI interface

Contextual Info: STC5420 Synchronous Clock for SETS Data sheet Description Features The RoHS 6/6 compliant STC5420 is a single chip clock synchronization solution for applications in SDH/SETS, SONET, and Synchronous Ethernet network elements. The device is fully compliant with ITU-T G.813 option 1 and 2,

history of automatic phase selector

Contextual Info: STC5420 Synchronous Clock for SETS Data sheet Description Features The RoHS 6/6 compliant STC5420 is a single chip clock synchronization solution for applications in SDH/SETS, SONET, and Synchronous Ethernet network elements. The device is fully compliant with ITU-T G.813 option 1 and 2,

4092MHz

Abstract: 12276M gps clock
Contextual Info: STA5620 Fully integrated RF front-end receiver for GPS applications Preliminary Data Features • Low IF architecture fIF = 4fO ■ Minimum external components ■ VGA gain internally regulated ■ On chip programmable PLL ■ Typ. 2.7V supply voltage ■

Contextual Info: STC5420 Synchronous Clock for SETS Data sheet Description Features The RoHS 6/6 compliant STC5420 is a single chip clock synchronization solution for applications in SDH/SETS, SONET, and Synchronous Ethernet network elements. The device is fully compliant with ITU-T G.813 option 1 and 2,

china model inverter circuit diagram

Abstract: STA5620 tcxo 16.368MHz 2.7V QFN-32 STA5620TR gps clock
Contextual Info: STA5620 Fully integrated RF front-end for GPS Preliminary Data Features • Low IF architecture fIF = 4fO ■ Minimum external components ■ VGA gain internally regulated ■ On chip programmable PLL ■ Typ. 2.7V supply voltage ■ SPI interface ■ 2kV HBM ESD protected

STA5620

Abstract: QFN-32 STA5620TR VFQFPN32
Contextual Info: STA5620 Fully integrated RF front-end receiver for GPS applications Features • Low IF architecture fIF = 4fO ■ Minimum external components ■ VGA gain internally regulated ■ On chip programmable PLL ■ Typ. 2.7 V supply voltage ■ SPI interface

Contextual Info: STA5620A STA5620C Fully integrated RF front-end receiver for GPS applications Features • Low IF architecture fIF = 4fO ■ Minimum external components ■ VGA gain internally regulated ■ On chip programmable PLL ■ Typ. 2.7 V supply voltage ■ SPI interface

STA5620C

Contextual Info: STA5620A STA5620C Fully integrated RF front-end receiver for GPS applications Features • Low IF architecture fIF = 4fO ■ Minimum external components ■ VGA gain internally regulated ■ On chip programmable PLL ■ Typ. 2.7 V supply voltage ■ SPI interface

Contextual Info: STA5620 Fully integrated RF front-end receiver for GPS applications Features • Low IF architecture fIF = 4fO ■ Minimum external components ■ VGA gain internally regulated ■ On chip programmable PLL ■ Typ. 2.7 V supply voltage ■ SPI interface

Contextual Info: STC5423 Synchronous Clock for SETS Data sheet Description Features The RoHS 6/6 compliant STC5423 is a single chip clock synchronization solution for applications in SDH/SETS, SONET, and Synchronous Ethernet network elements. The device is fully compliant with ITU-T G.813 option 1 and 2,

Contextual Info: STC5423 Synchronous Clock for SETS Data sheet Description Features The RoHS 6/6 compliant STC5423 is a single chip clock synchronization solution for applications in SDH/SETS, SONET, and Synchronous Ethernet network elements. The device is fully compliant with ITU-T G.813 option 1 and 2,

tm114

Contextual Info: STC5423 Synchronous Clock for SETS Data sheet Description Features The RoHS 6/6 compliant STC5423 is a single chip clock synchronization solution for applications in SDH/SETS, SONET, and Synchronous Ethernet network elements. The device is fully compliant with ITU-T G.813 option 1 and 2,

Contextual Info: STC5423 Synchronous Clock for SETS Data sheet Description Features The RoHS 6/6 compliant STC5423 is a single chip clock synchronization solution for applications in SDH/SETS, SONET, and Synchronous Ethernet network elements. The device is fully compliant with ITU-T G.813 option 1 and 2,

JMP19

Abstract: SK3 lamp SW-DIP-2 C5659 jmp20 EPM7128STC100-15 panel mount banana jack smd pushbutton footprint P200 ACS8947T
Contextual Info: ACS8947T JAM PLL Jitter Attenuating, Multiplying Phase-Locked Loop with Automatic Input Switch and Data Resynchronization Path ADVANCED COMMUNICATIONS COMMS & SENSING FINAL EVALUATION BOARD ACS8947T JAM PLL Evaluation Board EVB Kit About this document This document is the user guide for the ACS8947T JAM

Contextual Info: EV8AQ165A QUADRUPLE Analog to Digital Converter High Bandwith, Low power, Low input Swing QUAD 8-bit 1.25 GSps ADC operting up to 5 GSps Datasheet Main Features • Quad ADC with 8-bit Resolution using e2v Proprietary Analog input Cross-point Switch • •

SAA7119

Abstract: saa7154 RSN 309 W 44H SAA7154H SAA7154E SAA7118 An RTCO 7AH SPLPL9 myson mtv048 SAA7154E/V2
Contextual Info: SAA7154E; SAA7154H Multistandard video decoder with comb filter, component input and RGB output Rev. 02 — 6 December 2007 Product data sheet 1. General description The SAA7154E; SAA7154H is a high-quality multistandard video decoder supporting 10-bit Analog-to-Digital Converter ADC , enhanced PAL/NTSC comb filtering, more

TFBGA48 thermal

Contextual Info: STA529 FFX audio codec with analog and digital inputs and 2 x 1.2 W or 2 x 100 mW HP class-D amplifier Datasheet − production data Features • Up to 96 dB dynamic range ■ Sample rates from 8 kHz to 192 kHz ™ TFBGA48 ■ FFX ■ 1.55 V to 1.95 V digital power supply

Contextual Info: STA529 FFX audio codec with analog and digital inputs and 2 x 1.2 W or 2 x 100 mW HP class-D amplifier Datasheet − production data Features • Up to 96 dB dynamic range ■ Sample rates from 8 kHz to 192 kHz ™ TFBGA48 ■ FFX ■ 1.55 V to 1.95 V digital power supply

STA529

Abstract: adc/microphone converter P2SC STA529Q TFBGA48 10 pin volume control
Contextual Info: STA529 FFX audio codec with analog and digital inputs and 2 x 1.2 W or 2 x 100 mW HP class-D amplifier Features „ Up to 96 dB dynamic range „ Sample rates from 8 kHz to 192 kHz „ FFX™ class-D driver „ 1.55 V to 1.95 V digital power supply „ 1.80 V to 3.60 V analog and I/O power supply