HEX GATE OR AND Search Results

14572U

Contextual Info: H D 14572U B Hex Gate 4 - ln v e r e r 2 - i n p u t NOR Gate 2 - i n p u t N A N D Gate The HD14572UB hex functional gate finds primary use where low power dissipation and/or high noise immunity is desired. The chip contains four inverters, one NOR gate and one NAND gate.

MC14572UB

Abstract: MC14572UBCP MC14572UBD MC14572UBDR2 MC14572UBF MC14572UBFEL 14572U
Contextual Info: MC14572UB Hex Gate The MC14572UB hex functional gate is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. These complementary MOS logic gates find primary use where low power dissipation and/or high noise immunity

MC14572U

Abstract: 14572ubg
Contextual Info: MC14572UB Hex Gate The MC14572UB hex functional gate is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. These complementary MOS logic gates find primary use where low power dissipation and/or high noise immunity

135VDC

Abstract: MC14572UBCP MC14572UB MC14572UBD MC14572UBDR2 MC14572UBF MC14572UBFEL 14572U
Contextual Info: MC14572UB Hex Gate The MC14572UB hex functional gate is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. These complementary MOS logic gates find primary use where low power dissipation and/or high noise immunity

Contextual Info: MC14572UB Hex Gate The MC14572UB hex functional gate is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. These complementary MOS logic gates find primary use where low power dissipation and/or high noise immunity

MC14572

Abstract: MC14572UB MC14572UBCP MC14572UBCPG MC14572UBD MC14572UBDG MC14572UBDR2 MC14572UBDR2G MC14572UBF 14572u
Contextual Info: MC14572UB Hex Gate The MC14572UB hex functional gate is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. These complementary MOS logic gates find primary use where low power dissipation and/or high noise immunity

serial number of idm

Abstract: HIP0061 HIP0063 HIP0063AB MS-013-AE
Contextual Info: HIP0063 PRELIMINARY Hex Low Side MOSFET Driver with Serial or Parallel Interface and Diagnostic Fault Control October 1995 Features Description • Six Channel MOSFET Driver with Gate Drive Control by Serial SPI or Parallel Interface and an Option for PWM Logic Switching Control

NTE4511B

Abstract: Q32B NTE4501 NTE4518B NTE4520B NTE4508B NTE4510B NTE4512B NTE4514B NTE4516B
Contextual Info: INTEGRATED CIRCUITS - CMOS COMPLEMENTARY METAL OXIDE SILICON NTE4501 16 -L e a d DI P, See D iag. 249 Dual 4 -In p u t N AND Gate, 2 -In p u t NOR/OR Gate, 8 -In p u t AN D/NAN D Gate NTE4502B 1 6-L e a d DIP, See Dlag. 249 Strobed Hex Inverter/Buffer N TE4503B

DM54L04J

Abstract: block diagram of AND gate C1995 DM54L04 DM54L04W J14A W14B
Contextual Info: DM54L04 Hex Inverting Gate General Description This device contains six independent gates each of which performs the logic INVERT function Connection Diagram Dual-In-Line Package TL F 6616 – 1 Order Number DM54L04J or DM54L04W See NS Package Number J14A or W14B

Contextual Info: SN74AS1832 HEX 2-INPUT OR DRIVER SDAS045C – AUGUST 1984 – REVISED JANUARY 1995 • • D OR N PACKAGE TOP VIEW High Capacitive-Drive Capability Typical Delay Time of 3.9 ns (CL = 50 pF) and Typical Power Dissipation of Less Than 17 mW per Gate Center VCC and GND Configuration

Contextual Info: SN74AS1832 HEX 2-INPUT OR DRIVER SDAS045C – AUGUST 1984 – REVISED JANUARY 1995 • • D OR N PACKAGE TOP VIEW High Capacitive-Drive Capability Typical Delay Time of 3.9 ns (CL = 50 pF) and Typical Power Dissipation of Less Than 17 mW per Gate Center VCC and GND Configuration

Contextual Info: SN74AS1832 HEX 2-INPUT OR DRIVER S0ASQ4SC - AUGUST 1984 - REVISED JANUARY 1995 High Capacltlve-Drlve Capability 0 OR N PACKAGE TOP VIEW Typical Delay Time of 3.9 ns (C l = 50 pF) and typical Power Dissipation of Less Than 17 mW per Gate Center \ I q q and GND Configuration

SN74AS1832

Contextual Info: SN74AS1832 HEX 2-INPUT OR DRIVER SDAS045C – AUGUST 1984 – REVISED JANUARY 1995 • • D OR N PACKAGE TOP VIEW High Capacitive-Drive Capability Typical Delay Time of 3.9 ns (CL = 50 pF) and Typical Power Dissipation of Less Than 17 mW per Gate Center VCC and GND Configuration

Contextual Info: SN74AS1832 HEX 2ĆINPUT OR DRIVER ą SDAS045C − AUGUST 1984 − REVISED JANUARY 1995 • • D OR N PACKAGE TOP VIEW High Capacitive-Drive Capability Typical Delay Time of 3.9 ns (CL = 50 pF) and Typical Power Dissipation of Less Than 17 mW per Gate Center VCC and GND Configuration

Contextual Info: LS365 Hex 3-State Buffer with Common 2-Input NOR Enable Gate The LS365 is a bipolar, NPN, sealed-junction, silicon integrated circuit. It is manufactured in lowpower Schottky technology and is available in a wire-bonded, 16-pin plastic DIP or surface mount

SN74AS1805

Contextual Info: SN74AS1805 HEX 2ĆINPUT NOR DRIVER ą SDAS043C − AUGUST 1984 − REVISED JANUARY 1995 • • DW OR N PACKAGE TOP VIEW High Capacitive-Drive Capability Typical Delay Time of 2.6 ns (CL = 50 pF) and Typical Power Dissipation of Less Than 12 mW Per Gate

A114

Abstract: MC74VHC04 MC74VHC1G04 MC74VHC1GU04 MC74VHCU04
Contextual Info: MC74VHC1GU04 Single Unbuffered Inverter The MC74VHC1GU04 is an advanced high speed CMOS Unbuffered inverter fabricated with silicon gate CMOS technology. This device consists of a single unbuffered inverter. In combination with others, or in the MC74VHCU04 Hex Unbuffered Inverter, these

A114

Abstract: MC74VHC04 MC74VHC1G04 MC74VHC1GU04 MC74VHCU04 U1500
Contextual Info: MC74VHC1GU04 Single Unbuffered Inverter The MC74VHC1GU04 is an advanced high speed CMOS Unbuffered inverter fabricated with silicon gate CMOS technology. This device consists of a single unbuffered inverter. In combination with others, or in the MC74VHCU04 Hex Unbuffered Inverter, these

KK74ACT174

Abstract: KK74ACT174D KK74ACT174N
Contextual Info: TECHNICAL DATA KK74ACT174 Hex D Flip-Flop with Common Clock and Reset High-Speed Silicon-Gate CMOS The KK74ACT174 is identical in pinout to the LS/ALS174, HC/HCT174. The KK74ACT174 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs.

IN74ACT174D

Abstract: IN74ACT174N
Contextual Info: TECHNICAL DATA IN74ACT174 Hex D Flip-Flop with Common Clock and Reset High-Speed Silicon-Gate CMOS The IN74ACT174 is identical in pinout to the LS/ALS174, HC/HCT174. The IN74ACT174 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs.

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA M C74HCT04A Hex Inverter With LSTTL-Compatible Inputs High-Performance Silicon-Gate CMOS The MC74HCT04A may be used as a level converter for interfacing TTL or NMOS outputs to H igh-S peed CMOS inputs. N SUFFIX PLASTIC PACKAGE

KK74HCT14A

Abstract: KK74HCT14AD KK74HCT14AN
Contextual Info: TECHNICAL DATA KK74HCT14A Hex Schmitt-Trigger Inverter High-Performance Silicon-Gate CMOS The KK74HCT14A may be used as a level converter for interfacing TTL or NMOS outputs to high-speed CMOS inputs. The KK74HCT14A is identical in pinout to the LS/ALS14.

48-mA

Abstract: SN74AS1804
Contextual Info: SN74AS1804 HEX 2-INPUT NAND DRIVER SDAS042C – AUGUST 1984 – REVISED JANUARY 1995 • • DW OR N PACKAGE TOP VIEW High Capacitive-Drive Capability Typical Delay Time of 2.6 ns (CL = 50 pF) and Typical Power Dissipation of Less Than 9 mW Per Gate Center VCC and GND Configuration

Contextual Info: SN74AS1804 HEX 2-INPUT NAND DRIVER SDAS042C – AUGUST 1984 – REVISED JANUARY 1995 • • DW OR N PACKAGE TOP VIEW High Capacitive-Drive Capability Typical Delay Time of 2.6 ns (CL = 50 pF) and Typical Power Dissipation of Less Than 9 mW Per Gate Center VCC and GND Configuration