H.261 ENCODER CHIP Search Results

Contextual Info: VP2611 JANUARY 1996 ADVANCE INFORMATION DS3478 - 3.0 VP2611 H.261 ENCODER Supersedes version in June 1995 Digital Video & DSP IC Handbook, HB3923-2 FEATURES DESCRIPTION • Fully integrated H261 video encoder ■ Up to full CIF resolution and 30 Hz frame rates

VP510

Abstract: VP520 VP520S DS3487 H261 VP2611 VP2612 VP2614 VP2615 PAL colour coder block diagram
Contextual Info: VP2611 VP2611 H.261 Encoder Supersedes June 1996 edition, DS3487 - 4.0 DS3487 - 4.1 December 1998 FEATURES DESCRIPTION • Fully integrated H261 video encoder ■ Up to full CIF resolution and 30 Hz frame rates ■ Inputs YUV data in 8 x 8 sub block format

Contextual Info: VP2611 VP2611 H.261 Encoder Supersedes June 1996 edition, DS3487 - 4.0 DS3487 - 4.1 December 1998 FEATURES DESCRIPTION • Fully integrated H261 video encoder ■ Up to full CIF resolution and 30 Hz frame rates ■ Inputs YUV data in 8 x 8 sub block format

DS3487

Abstract: H261 VP2611 VP2612 VP2614 VP2615 VP510 VP520 VP520S
Contextual Info: VP2611 VP2611 H.261 Encoder Supersedes June 1996 edition, DS3487 - 4.0 DS3487 - 4.1 December 1998 FEATURES DESCRIPTION • Fully integrated H261 video encoder ■ Up to full CIF resolution and 30 Hz frame rates ■ Inputs YUV data in 8 x 8 sub block format

DS3487

Abstract: H261 VP2611 VP2612 VP2614 VP2615 VP510 VP520 VP520S
Contextual Info: VP2611 VP2611 H.261 Encoder Supersedes June 1996 edition, DS3487 - 4.0 DS3487 - 4.1 December 1998 FEATURES DESCRIPTION • Fully integrated H261 video encoder ■ Up to full CIF resolution and 30 Hz frame rates ■ Inputs YUV data in 8 x 8 sub block format

Contextual Info: S i GEC PLESSEY ADVANCE INFORMATION SEMI CONDUCTORS VP2611 H.261 ENCODER Supersedes version in December 1993 Digital Video S DSP 1C Handbook, H83923-1 FEATURES DESCRIPTION • Fully integrated H261 video encoder ■ Up to full CIF resolution and 30 Hz 1rame rates

DS3487

Abstract: H261 VP2611 VP2612 VP2614 VP2615 VP510 VP520 VP520S 1996 yuv rgb conversion frame buffer
Contextual Info: VP2611 VP2611 H.261 Encoder Supersedes June 1996 edition, DS3487 - 4.0 DS3487 - 4.1 December 1998 FEATURES DESCRIPTION • Fully integrated H261 video encoder ■ Up to full CIF resolution and 30 Hz frame rates ■ Inputs YUV data in 8 x 8 sub block format

MACROBIOCK

Contextual Info: MITEL VP2611 _ H.261 Encoder QPvynrnMni inrm o Supersedes June 1996 edition, DS3487 - 4.0 DS3487 - 4.1 December 1998 FEATURES DESCRIPTION • Fully integrated H261 video encoder ■ Up to full CIF resolution and 30 Hz fram e rates ■ Inputs YUV data in 8 x 8 sub block form at

Contextual Info: J'îV ’ ' 31 G F C Pi FSSFY JUNE 1993 S l M I C: « N l U C T l) K S PRELIMINARY INFORMATION DS3478 • 1.4 VP 2611 H .261 ENCODER FEATURES DESCRIPTION I Fully integrated H261 video encoder H Up to full CIF resolution and 30 Hz frame rates H Inputs YUV data in 8 x 8 sub block format

Contextual Info: VP2611 @ M ITEL H.261 Encoder SE M IC O N D U C T O R Supersedes January 1996 edition, DS3487 - 3.0 DS3487 - 4.0 June 1996 FEATURES DESCRIPTION • Fully integrated H261 video encoder ■ Up to full CIF resolution and 30 Hz frame rates ■ Inputs YUV data in 8 x 8 sub block format

Contextual Info: M ITEL VP2611 _ H.261 Encoder SE M IC O N D U C T O R Supersedes January 1996 edition, DS3487 - 3.0 DS3487 - 4.0 June 1996 FEATURES DESCRIPTION • Fully integrated H261 video encoder ■ Up to full CIF resolution and 30 Hz frame rates ■ Inputs YUV data in 8 x 8 sub block format

Contextual Info: VP2611 H.261 Encoder S E M IG O tV ID L IO lfO ß Supersedes June 1996 edition, DS3487 - 4.0 DS3487 - 4.1 December 1998 FEATURES DESCRIPTION • Fully integrated H261 video encoder ■ Up to full CIF resolution and 30 Hz fram e rates ■ Inputs YUV data in 8 x 8 sub block form at

gc132

Contextual Info: a i GEC PLESSEY SEPTEMBER 1994 PRELIMINARY INFORMATION S E M I C O N D U C T O R S DS3478 - 2.3 VP2611 H.261 ENCODER Supersedes version in December 1993 Digital Video & DSP 1C Handbook, HB3923-1 DESCRIPTION FEATURES Fully integrated H261 video encoder Up to full CIF resolution and 30 Hz frame rates

Contextual Info: LSI LOGIC L64715 Two-Error Correcting BCH Encoder-Decoder Description The L64715 implements the forw ard error co r­ rection, bit filling and synchronization scheme specified in CCITT Consultative Committee on International Telephones and Telegraphs recom m endation H.261. The forw ard error

Contextual Info: LSI LOGIC L64715 Two-Error Correcting BCH Encoder-Decoder Description The L64715 implements the forw ard error co r­ rection, bit filling and synchronization schem e specified in ITU-TSS formerly CCITT recom m endation H.261. The forw ard error correcting code is a 2-error correcting BCH

BCH code

Contextual Info: LSI LOGIC L64715 Two-Error Correcting BCH Encoder-Decoder Description The L64715 implements the forw ard error cor­ rection, bit filling and synchronization schem e specified in IT U -T SS formerly CCITT recom m endation H.261. The forward error correcting code is a 2-error correcting BCH

H.261 encoder chip

Contextual Info: VPB261 H.261 Evaluation Board Application Note AN146 - 2.1 June 1996 FEATURES EVALUATION BOARD OVERVIEW • Complete evaluation and prototyping system for Mitel Semiconductor H.261 Video Compression/Decompression chipset. RGB format video is input to the board from a source which

Contextual Info: HMP8364 h a r r is S E M I C O N D U C T O R Ê Ê Ë W Ë È PRELIMINARY H.261 Video CODEC June 1997 Features Description • Com plete and Fully Com pliant H.261 Codec Including Framing and BCH Error Detect/Correct The Harris H.261 Video Codec is a single-chip, high perfor­

dwa 108 a

Abstract: 27mhz remote control IC H261 HMP8112 HMP8364 MD31 dwa 108 Variable Length Decoder VLD
Contextual Info: HMP8364 S E M I C O N D U C T O R PRELIMINARY H.261 Video CODEC June 1997 Features Description • Complete and Fully Compliant H.261 Codec Including Framing and BCH Error Detect/Correct The Harris H.261 Video Codec is a single-chip, high performance integrated circuit that simultaneously encodes and

Contextual Info: HMP8364 S E M IC O N D U C T O R PRELIMINARY H.261 Video CODEC June 1997 Features Description • Complete and Fully Compliant H.261 Codec Including Framing and BCH Error Detect/Correct The Harris H.261 Video Codec is a single-chip, high perfor­ mance integrated circuit that simultaneously encodes and

H.261

Abstract: Video controller TMS320C80 videostream decoders 1995 jpeg codec mean absolute difference TMS320C80 H.261 encoder chip H261
Contextual Info: H.261 Implementation on the TMS320C80 DSP Application Report 1997 Digital Signal Processing Solutions Printed in U.S.A., June 1997 SPRA161 H.261 Implementation on the TMS320C80 DSP Application Report SPRA161 June 1997 Printed on Recycled Paper IMPORTANT NOTICE

ECHO canceller IC

Abstract: h221 HMP8112 HMP8112A HMP8156 HMP8201 HMP8320VCS HMP8364
Contextual Info: HMP8320VCS S E M I C O N D U C T O R ADVANCE INFORMATION Video Conference Solution Chip Set June 1997 Features Description • Fully Compliant with ITU-T H.320 The HMP8320VCS Video Conference Solution chip set is fully compliant with the ITU-T H.320 Teleconferencing standard and designed to run with a host processor. The VCS

ti 261

Abstract: PX-64 motion camera h261 TMS320C80 TMS320C82 Video controller TMS320C80 H.261 encoder chip mean absolute difference H.261 decoder chip
Contextual Info: H.261 Implementation on the TMS320C80 DSP Application Report 1997 Digital Signal Processing Solutions Printed in U.S.A., June 1997 SPRA161 H.261 Implementation on the TMS320C80 DSP Application Report SPRA161 June 1997 Printed on Recycled Paper IMPORTANT NOTICE

TMS320C80

Abstract: H.261 encoder chip H261 TMS320C82 mpeg coder audio layer 2 at&t video decoder mpeg
Contextual Info: H.261 Implementation on the TMS320C80 DSP Application Report 1997 Digital Signal Processing Solutions Printed in U.S.A., June 1997 SPRA161 H.261 Implementation on the TMS320C80 DSP Application Report SPRA161 June 1997 Printed on Recycled Paper IMPORTANT NOTICE