GX MARK Search Results

S82451KX

Abstract: s82452kx S82454GX s82453kx 450GX 450KX 82453KX 243109 d655 s-spec
Contextual Info: Intel 450KX/GX PCIset Specification Update 82454KX/GX PB 82453KX/GX (MC) 82452KX/GX (DP) 82451KX/GX (MIC) Release Date: April 1998 Order Number: 243109-014 The Intel 450KX/GX PCIset may contain design defects or errors known as errata which may cause the product

U042

Abstract: S82454GX 450GX 450KX 82453KX S82451KX 243109 S82451GX 82451KX
Contextual Info: Intel 450KX/GX PCIset Specification Update 82454KX/GX PB 82453KX/GX (MC) 82452KX/GX (DP) 82451KX/GX (MIC) Release Date: October 1997 Order Number: 243109-012 The 450KX/GX PCIset may contain design defects or errors known as errata which may cause the product to

450GX

Abstract: S82454GX 3014 LED 82450 S82452GX S82454 3554-1 pciset datasheet S82451GX U056
Contextual Info: Intel 450KX/GX PCIset Specification Update 82454KX/GX PB 82453KX/GX (MC) 82452KX/GX (DP) 82451KX/GX (MIC) Release Date: August 1998 Order Number: 243109-015 The Intel 450KX/GX PCIset may contain design defects or errors known as errata which may cause the product

10-bit-serdes

Abstract: K280A B010011 8HBC D243
Contextual Info: 2. Stratix II GX Transceiver Architecture Overview SIIGX52002-4.1 Introduction This chapter provides detailed information about the architecture of Stratix II GX devices. Figure 2–1 shows the Stratix II GX block diagram. Figure 2–1. Stratix II GX Transceiver Block Diagram

ddr dimm pinout

Abstract: L1238 socket am3 pinout j8510 fairchild aa11 MDIO clause 22 J124 J68 10A intel D915 xcvr
Contextual Info: Stratix GX Development Board Data Sheet August 2003, ver. 1.1 Designers can use the Stratix GX Development Board to prototype and develop high-speed applications for StratixTM GX and StratixTM FPGAs. Use of this board can shorten the time to market for applicable designs.

EP2SGX60EF

Abstract: CEI 23-16 circuit diagram of PPM transmitter and receiver CPRI multi rate HD-SDI over sdh PRBS10 3G-SDI serializer SIIGX52002-4 k307
Contextual Info: 2. Stratix II GX Transceiver Architecture Overview SIIGX52002-4.2 Introduction This chapter provides detailed information about the architecture of Stratix II GX devices. Figure 2–1 shows the Stratix II GX block diagram. Figure 2–1. Stratix II GX Transceiver Block Diagram

AN328

Abstract: AP1910 MT47H64M16BT-37E MT47H32M16CC-3 AL1510 EP2SGX90FF1508C3 AL15-10 MT47H64M8CB-3 MT47H64M16 MT47H64M16BT-37E eye
Contextual Info: AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria GX Devices October 2009 AN-328-6.0 Introduction This application note provides information about interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria ® GX devices. It includes details about supported modes and

texas handbook

Abstract: 1008-B
Contextual Info: Section I. Stratix II GX Transceiver User Guide This section provides information on the configuration modes for Stratix II GX devices. It also includes information on testing, Stratix II GX port and parameter information, and pin constraint information.

video transmiter

Abstract: hd sdi receiver DDR333 EPC16 MK2069 27mhz transmitter and receiver hd receiver 27mhz transmitter 27mhz receiver 20 pin header connector
Contextual Info: Stratix GX Video Demonstration Board Data Sheet May 2004, version 1.0 Introduction f The Altera Stratix® GX Video Demonstration Board is an evaluation platform that demonstrates the superior video performance and key features of Altera’s Stratix GX devices. The Stratix GX board and Altera’s

EP4SGX230

Abstract: EP4SGX180 EP4SGX290 EP4SGX360 EP4SGX70 receiver altLVDS EP4SGX230ES
Contextual Info: Errata Sheet for Stratix IV GX Devices ES-01022-5.5 Errata Sheet This errata sheet provides updated information about known device issues affecting Stratix IV GX devices. Production Devices for Stratix IV GX Devices Table 1 lists the specific issues and the affected Stratix IV GX production devices.

HD-SDI over sdh

Abstract: GR-253-CORE PRBS31 SMPTE292M SSTL-15 SSTL-18 PRBS-15
Contextual Info: Section I. Arria II GX Device Data Sheet and Addendum This section provides information about the Arria II GX device data sheet and addendum. This section includes the following chapters: • Chapter 1, Arria II GX Device Datasheet ■ Chapter 2, Addendum to the Arria II GX Device Handbook

Contextual Info: Section I. Arria II GX Device Data Sheet and Addendum This section provides information about the Arria II GX device data sheet and addendum. This section includes the following chapters: • Chapter 1, Arria II GX Devices Data Sheet ■ Chapter 2, Addendum to the Arria II GX Device Handbook

AGX52007-1

Abstract: SSTL-18
Contextual Info: 7. External Memory Interfaces in Arria GX Devices AGX52007-1.0 Introduction ArriaTM GX devices support external memory interfaces, including DDR SDRAM, DDR2 SDRAM, and SDR SDRAM. Its dedicated phase-shift circuitry allows the Arria GX device to interface with an external memory

free verilog code of prbs pattern generator

Abstract: CPRI multi rate digital alarm clock vhdl code 10 band graphic equalizer CEI 23-16 diode handbook HD-SDI over sdh SDH 209 vhdl code for 16 prbs generator vhdl code for phase frequency detector for FPGA
Contextual Info: Section I. Stratix II GX Transceiver User Guide This section provides information on the configuration modes for Stratix II GX devices. It also includes information on testing, Stratix II GX port and parameter information, and pin constraint information.

B17C

Abstract: Chapter 3 Synchronization diode handbook SDI SERIALIZER Semiconductor Reference and Application Handbook AGX52001-2 Voltage-controlled oscillator hd-SDI deserializer LVDS EP1AGX50DF
Contextual Info: Section I. Arria GX Transceiver User Guide This section provides information on the configuration modes for Arria GX devices. It also includes information on testing, Arria GX port and parameter information, and pin constraint information. This section includes the following chapters:

EP2AGX125

Abstract: ALTMEMPHY
Contextual Info: Arria II GX Device Family ES-01025-3.1 Errata Sheet Introduction This errata sheet provides updated information about known device issues affecting Arria II GX devices. Table 1 lists the specific issues and which Arria II GX devices are affected by each

circuit diagram of inverting adder

Abstract: KR 108 6621 3.3V
Contextual Info: Stratix GX FPGA Family Data Sheet December 2004, ver. 2.2 Introduction The Stratix GX family of devices is Altera’s second FPGA family to combine high-speed serial transceivers with a scalable, high-performance logic array. Stratix GX devices include 4 to 20 high-speed transceiver

b17c

Abstract: AGX52001-1 AGX52002-1 PMD 1000
Contextual Info: Section I. Arria GX Transceiver User Guide This section provides information on the configuration modes for Arria GX devices. It also includes information on testing, Arria GX port and parameter information, and pin constraint information. This section includes the following chapters:

SSTL-18

Contextual Info: Stratix GX November 2002, ver. 1.0 Introduction FPGA Family Data Sheet Preliminary Information The StratixTM GX family of devices is Altera’s second FPGA family to combine high-speed serial transceivers with a scalable, high-performance logic array. Stratix GX devices include 4 to 20 high-speed transceiver

Contextual Info: 795 FIBER SENSORS Cylindrical Inductive Proximity Sensor Amplifier Built-in GX-U SERIES GX-FU SERIES GX-N SERIES Related Information •■General terms and conditions. F-17 ■■Glossary of terms. P.1386~ ■■Sensor selection guide. P.757~

obsai

Abstract: EP1AGX50CF484C6
Contextual Info: Arria GX Family Press FAQ What is the Arria GX FPGA family? The Arria GX family is comprised of Altera’s 90-nm low cost, transceiver-based FPGAs. The devices are optimized for the mainstream serial protocols from 600 Mbps up to 3.125 Gbps. Five family members range from 21,580 to 90,220 logic elements LEs . The Arria GX family is

AN-247

Abstract: Altera Stratix V AN247
Contextual Info: Stratix GX to Mercury Interoperability November 2002, ver. 1.0 Introduction Application Note 247 The introduction of the StratixTM GX device family enables a new level of integration by combining 3.125-gigabits per second Gbps transceivers with a high-performance FPGA core. The Stratix GX family is the

gxb tx_coreclk

Abstract: Altera 8b10b
Contextual Info: Stratix GX FPGA Errata Sheet July 2007, ver. 1.6 Introduction This document addresses transceiver-related known errata for the Stratix GX FPGA family production devices. 1 Receiver Phase Compensation FIFO For more information on Stratix GX device errata, refer to the

LHF16J06

Abstract: EPC16 0x00010040
Contextual Info: 2. Remote System Configuration with Stratix & Stratix GX Devices S52015-3.1 Introduction Altera Stratix® and Stratix GX devices are the first programmable logic devices PLDs featuring dedicated support for remote system configuration. Using remote system configuration, a Stratix or Stratix GX