S82451KX
Abstract: s82452kx S82454GX s82453kx 450GX 450KX 82453KX 243109 d655 s-spec
Contextual Info: Intel 450KX/GX PCIset Specification Update 82454KX/GX PB 82453KX/GX (MC) 82452KX/GX (DP) 82451KX/GX (MIC) Release Date: April 1998 Order Number: 243109-014 The Intel 450KX/GX PCIset may contain design defects or errors known as errata which may cause the product
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S82451KX
s82452kx
S82454GX
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450GX
450KX
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d655
s-spec
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U042
Abstract: S82454GX 450GX 450KX 82453KX S82451KX 243109 S82451GX 82451KX
Contextual Info: Intel 450KX/GX PCIset Specification Update 82454KX/GX PB 82453KX/GX (MC) 82452KX/GX (DP) 82451KX/GX (MIC) Release Date: October 1997 Order Number: 243109-012 The 450KX/GX PCIset may contain design defects or errors known as errata which may cause the product to
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450KX/GX
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82453KX/GX
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82451KX/GX
U042
S82454GX
450GX
450KX
82453KX
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243109
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82451KX
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10-bit-serdes
Abstract: K280A B010011 8HBC D243
Contextual Info: 2. Stratix II GX Transceiver Architecture Overview SIIGX52002-4.1 Introduction This chapter provides detailed information about the architecture of Stratix II GX devices. Figure 2–1 shows the Stratix II GX block diagram. Figure 2–1. Stratix II GX Transceiver Block Diagram
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SIIGX52002-4
8B/10B
10-bit-serdes
K280A
B010011
8HBC
D243
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EP2SGX60EF
Abstract: CEI 23-16 circuit diagram of PPM transmitter and receiver CPRI multi rate HD-SDI over sdh PRBS10 3G-SDI serializer SIIGX52002-4 k307
Contextual Info: 2. Stratix II GX Transceiver Architecture Overview SIIGX52002-4.2 Introduction This chapter provides detailed information about the architecture of Stratix II GX devices. Figure 2–1 shows the Stratix II GX block diagram. Figure 2–1. Stratix II GX Transceiver Block Diagram
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EP2SGX60EF
CEI 23-16
circuit diagram of PPM transmitter and receiver
CPRI multi rate
HD-SDI over sdh
PRBS10
3G-SDI serializer
k307
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texas handbook
Abstract: 1008-B
Contextual Info: Section I. Stratix II GX Transceiver User Guide This section provides information on the configuration modes for Stratix II GX devices. It also includes information on testing, Stratix II GX port and parameter information, and pin constraint information.
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video transmiter
Abstract: hd sdi receiver DDR333 EPC16 MK2069 27mhz transmitter and receiver hd receiver 27mhz transmitter 27mhz receiver 20 pin header connector
Contextual Info: Stratix GX Video Demonstration Board Data Sheet May 2004, version 1.0 Introduction f The Altera Stratix® GX Video Demonstration Board is an evaluation platform that demonstrates the superior video performance and key features of Altera’s Stratix GX devices. The Stratix GX board and Altera’s
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SMPTE-292M
SMPTE-259M
video transmiter
hd sdi receiver
DDR333
EPC16
MK2069
27mhz transmitter and receiver
hd receiver
27mhz transmitter
27mhz receiver
20 pin header connector
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EP4SGX230
Abstract: EP4SGX180 EP4SGX290 EP4SGX360 EP4SGX70 receiver altLVDS EP4SGX230ES
Contextual Info: Errata Sheet for Stratix IV GX Devices ES-01022-5.5 Errata Sheet This errata sheet provides updated information about known device issues affecting Stratix IV GX devices. Production Devices for Stratix IV GX Devices Table 1 lists the specific issues and the affected Stratix IV GX production devices.
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M9K/M144K
EP4SGX230
EP4SGX180
EP4SGX290
EP4SGX360
EP4SGX70
receiver altLVDS
EP4SGX230ES
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HD-SDI over sdh
Abstract: GR-253-CORE PRBS31 SMPTE292M SSTL-15 SSTL-18 PRBS-15
Contextual Info: Section I. Arria II GX Device Data Sheet and Addendum This section provides information about the Arria II GX device data sheet and addendum. This section includes the following chapters: • Chapter 1, Arria II GX Device Datasheet ■ Chapter 2, Addendum to the Arria II GX Device Handbook
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free verilog code of prbs pattern generator
Abstract: CPRI multi rate digital alarm clock vhdl code 10 band graphic equalizer CEI 23-16 diode handbook HD-SDI over sdh SDH 209 vhdl code for 16 prbs generator vhdl code for phase frequency detector for FPGA
Contextual Info: Section I. Stratix II GX Transceiver User Guide This section provides information on the configuration modes for Stratix II GX devices. It also includes information on testing, Stratix II GX port and parameter information, and pin constraint information.
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Contextual Info: Errata Sheet for Arria II GX Devices ES-01025-3.7 Errata Sheet This errata sheet provides updated information about known device issues affecting Arria II GX devices. Table 1 lists the specific issues and which Arria II GX devices are affected. Table 1. Issues for Arria II GX Devices Part 1 of 2
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B17C
Abstract: Chapter 3 Synchronization diode handbook SDI SERIALIZER Semiconductor Reference and Application Handbook AGX52001-2 Voltage-controlled oscillator hd-SDI deserializer LVDS EP1AGX50DF
Contextual Info: Section I. Arria GX Transceiver User Guide This section provides information on the configuration modes for Arria GX devices. It also includes information on testing, Arria GX port and parameter information, and pin constraint information. This section includes the following chapters:
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EP2AGX125
Abstract: ALTMEMPHY
Contextual Info: Arria II GX Device Family ES-01025-3.1 Errata Sheet Introduction This errata sheet provides updated information about known device issues affecting Arria II GX devices. Table 1 lists the specific issues and which Arria II GX devices are affected by each
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circuit diagram of inverting adder
Abstract: KR 108 6621 3.3V
Contextual Info: Stratix GX FPGA Family Data Sheet December 2004, ver. 2.2 Introduction The Stratix GX family of devices is Altera’s second FPGA family to combine high-speed serial transceivers with a scalable, high-performance logic array. Stratix GX devices include 4 to 20 high-speed transceiver
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b17c
Abstract: AGX52001-1 AGX52002-1 PMD 1000
Contextual Info: Section I. Arria GX Transceiver User Guide This section provides information on the configuration modes for Arria GX devices. It also includes information on testing, Arria GX port and parameter information, and pin constraint information. This section includes the following chapters:
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obsai
Abstract: EP1AGX50CF484C6
Contextual Info: Arria GX Family Press FAQ What is the Arria GX FPGA family? The Arria GX family is comprised of Altera’s 90-nm low cost, transceiver-based FPGAs. The devices are optimized for the mainstream serial protocols from 600 Mbps up to 3.125 Gbps. Five family members range from 21,580 to 90,220 logic elements LEs . The Arria GX family is
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AN-247
Abstract: Altera Stratix V AN247
Contextual Info: Stratix GX to Mercury Interoperability November 2002, ver. 1.0 Introduction Application Note 247 The introduction of the StratixTM GX device family enables a new level of integration by combining 3.125-gigabits per second Gbps transceivers with a high-performance FPGA core. The Stratix GX family is the
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LHF16J06
Abstract: EPC16 0x00010040
Contextual Info: 2. Remote System Configuration with Stratix & Stratix GX Devices S52015-3.1 Introduction Altera Stratix® and Stratix GX devices are the first programmable logic devices PLDs featuring dedicated support for remote system configuration. Using remote system configuration, a Stratix or Stratix GX
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phase shift
Abstract: AGX52007-1 SSTL-18
Contextual Info: 7. External Memory Interfaces in Arria GX Devices AGX52007-1.2 Introduction ArriaTM GX devices support external memory interfaces, including DDR SDRAM, DDR2 SDRAM, and SDR SDRAM. Its dedicated phase-shift circuitry allows the Arria GX device to interface with an external memory
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Hz/466
phase shift
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0X001F0000
Abstract: POF Formats Altera 0x00010040 stratus EPC16 LHF16J06
Contextual Info: 12. Remote System Configuration with Stratix & Stratix GX Devices S52015-3.1 Introduction Altera Stratix® and Stratix GX devices are the first programmable logic devices PLDs featuring dedicated support for remote system configuration. Using remote system configuration, a Stratix or Stratix GX
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stratus
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Altera hardcopy ASIC
Abstract: hard drive diagram
Contextual Info: Feature rich, easy to use, and low power PCI Express hard intellectual property solutions from Altera Altera’s 40-nm Stratix IV GX and Arria® II GX FPGAs and HardCopy® IV GX ASICs are all equipped with PCI Express hard IP blocks that are PCI-SIG compliant in supported configurations.
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Contextual Info: Serial Digital Interface Reference Design for Stratix V GX and Arria V GX Devices AN-668 Application Note Introduction The Serial Digital Interface SDI reference design shows how you can transmit and receive video data using the Altera SDI MegaCore® function, with the Stratix® V GX
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ADV1005
Abstract: EP2AGX45DF29C6N rh 115-2 EP2AGX95EF35I5N EP2AGX45DF29I5N EP2AGX65DF29I5N EP2AGX125EF29I3N EP2AGX65 EP2AGX45DF25C6N EP2AGX260FF35C4N
Contextual Info: Revision: 1.0.0 CUSTOMER ADVISORY ADV1005 ADDITIONAL ASSEMBLY SITE FOR THE ARRIA A II GX FBGA PACKAGE Change Description Altera will be introducing Amkor, Korea ATK as an additional assembly source for the Arria® II GX FBGA packagess. The Arria II GX family is currently manufactured out of Amkor,
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EP2AGX45DF29C6N
rh 115-2
EP2AGX95EF35I5N
EP2AGX45DF29I5N
EP2AGX65DF29I5N
EP2AGX125EF29I3N
EP2AGX65
EP2AGX45DF25C6N
EP2AGX260FF35C4N
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gxb tx_coreclk
Abstract: Altera 8b10b 8B10B 8b10b decoder
Contextual Info: Stratix GX FPGA October 2009 ES-STXGX-1.7 This document addresses transceiver-related known errata for the Stratix GX FPGA family production devices. 1 For more information on Stratix GX device errata, refer to the “Stratix Family Issues” section in the Stratix FPGA Family Errata Sheet.
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20-bit)
gxb tx_coreclk
Altera 8b10b
8B10B
8b10b decoder
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K277
Abstract: k27 equivalent altera stratix II fpga
Contextual Info: Stratix II GX FPGA Family Errata Sheet July 2007, ver. 1.1 Introduction This errata sheet provides updated information on Stratix II GX devices. This document addresses known device issues and includes methods to work around the issues. 1 For more information on Stratix II GX device errata, refer to the
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