GTL Search Results

Contextual Info: GTL1655, GTL1655 16-BIT LVTTL TO GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS WITH LIVE INSERTION SCBS696C - JULY 1997 - REVISED MAY 1998 Members of the Texas Instruments Widebus Family SN74G TL1655 . . . DGG PACKAGE TOP VIEW Translate Between GTL/GTL+ Signal Level

Contextual Info: GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER www.ti.com FEATURES • • • • • • • • • • • • Member of the Texas Instruments Widebus Family TI-OPC™ Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC™ Circuitry Improves Signal Integrity and

Contextual Info: GTLPH1616 17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS www.ti.com FEATURES • • • • • • • • • • • • • • • Member of the Texas Instruments Widebus Family UBT™ Transceiver Combines D-Type Latches

TSSOP20 FOOTPRINT

Abstract: SMD Transistor DN
Contextual Info: GTL2003 8-bit bidirectional low voltage translator Rev. 2 — 3 July 2012 Product data sheet 1. General description The Gunning Transceiver Logic - Transceiver Voltage Clamps GTL-TVC provide high-speed voltage translation with low ON-state resistance and minimal propagation

2N2007E

Abstract: 2N2007 CAP 10nF 50V 0603 18126D107MAT 597D108X06
Contextual Info: MIC5162 Dual Regulator Controller for DDR3 GDDR3/4/5 Memory and High-Speed Bus Termination General Description Features The MIC5162 is a dual regulator controller designed for highspeed bus termination. It offers a simple, low-cost JEDEC compliant solution for terminating high-speed, lowvoltage digital buses i.e. DDR, DD2, DDR3, SCSI, GTL,

msi 7267 MOTHERBOARD SERVICE MANUAL

Abstract: ttl cookbook msi ms 7267 MOTHERBOARD CIRCUIT diagram "0.4mm" bga "ball collapse" height PCF 799 crystal oscillator 8MHz 4 pins smd diode MARKING F5 44C smd TRANSISTOR code marking A7 terminals diagram of smd transistor bo2 cookbook for ic 555
Contextual Info: GTL/GTLP Logic High-Performance Backplane Drivers Data Book Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information

GTL2010

Abstract: GTL2010PW TSSOP24
Contextual Info: INTEGRATED CIRCUITS GTL2010 10-bit GTL Processor Voltage Clamp Product specification Philips Semiconductors 1999 Apr 05 Philips Semiconductors Product specification 10-bit GTL Processor Voltage Clamp FEATURES GTL2010 PIN CONFIGURATION • Direct interface with TTL level

AN10145

Abstract: GTL2000 GTL2010 GTL2010BS GTL2010PW HVQFN24 JESD22-A114 JESD22-A115 TSSOP24 smd transistor mark D10
Contextual Info: GTL2010 10-bit bidirectional low voltage translator Rev. 06 — 3 March 2008 Product data sheet 1. General description The Gunning Transceiver Logic - Transceiver Voltage Clamps GTL-TVC provide high-speed voltage translation with low ON-state resistance and minimal propagation

A115-A

Abstract: C101 SN74GTLP817 SN74GTLP817DW SN74GTLP817DWR
Contextual Info: GTLP817 GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER SCES285C – OCTOBER 1999 – REVISED FEBRUARY 2001 D D D D D D D D D D D D DGV, DW, OR PW PACKAGE TOP VIEW OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP

GTL2018PW

Abstract: JESD22-A114 JESD22-A115 JESD78 TSSOP24
Contextual Info: GTL2018 8-bit LVTTL to GTL transceiver Rev. 01 — 15 February 2007 Product data sheet 1. General description The GTL2018 is an octal translating transceiver designed for 3.3 V LVTTL system interface with a GTL−/GTL/GTL+ bus. The direction pin DIR allows the part to function as either a GTL-to-LVTTL sampling

Contextual Info: GTLPH32916 34-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS www.ti.com SCES380A – JANUARY 2002 – REVISED JUNE 2005 FEATURES • • • • • • • • Member of the Texas Instruments Widebus+ Family UBT™ Transceiver Combines D-Type Latches

Contextual Info: www.ti.com GTL16622A 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER SCBS673F – AUGUST 1996 – REVISED APRIL 2005 FEATURES • • • • • • • • • • Member of Texas Instruments Widebus Family OEC™ Circuitry Improves Signal Integrity and

Contextual Info: GTLPH32912 36-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER www.ti.com FEATURES • • • • • • • Member of the Texas Instruments Widebus+ Family UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, and

GTLP1B153

Abstract: GTLP1B153K8X GTLP1B153M GTLP1B153MX M08A MO-187
Contextual Info: Revised February 2002 GTLP1B153 1-Bit LVTTL/GTLP Driver/Receiver Pair General Description Features The GTLP1B153 is a 1-bit bus buffer pair with separate bit paths, that provide LVTTL-to-GTLP and GTLP-to-LVTTL signal level translation. High speed backplane operation is

A115-A

Abstract: C101 SN74GTL2007 26LVTTL
Contextual Info: GTL2007 12ĆBIT GTLĆ/GTL/GTL+ TO LVTTL TRANSLATOR SCLS609 − MARCH 2005 D Operates as a GTL-/GTL/GTL+ to LVTTL or D D D PW PACKAGE TOP VIEW LVTTL to GTL-/GTL/GTL+ Translator Series Termination on TTL Outputs of 30 W Latch-Up Testing Done to JEDEC Standard

Signal Path Designer

Contextual Info: GTLP2033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES352C – JUNE 2001 – REVISED SEPTEMBER 2001 D D D D D D D D D D D D D Member of the Texas Instruments Widebus Family TI-OPC Circuitry Limits Ringing on

Contextual Info: GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER www.ti.com FEATURES • • • • • • • • • • • • Member of the Texas Instruments Widebus Family TI-OPC™ Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC™ Circuitry Improves Signal Integrity and

5252 f 1110

Abstract: GTLP16612 GTLP16612MEA GTLP16612MTD MTD56
Contextual Info: co co ß O National Semiconductor PRELIMINARY GTLP16612 CMOS 18-Bit GTLP/TTL Universal Bus Transceiver General Description The GTLP16612 is one in a series of transceivers designed specifically for GTLP logic levels. The device is a CMOS GTLP 18-Bit registered bus transceivers which combines

A115-A

Abstract: C101 JESD-22 N2 SC70
Contextual Info: GTL3004 www.ti.com . SCBS873A – FEBRUARY 2008 – REVISED APRIL 2008 SELECTABLE GTL VOLTAGE REFERENCE FEATURES

A115-A

Abstract: C101 SN74GTLPH16927 SN74GTLPH16927GR
Contextual Info: GTLPH16927 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS www.ti.com SCES413 – OCTOBER 2002 – REVISED JUNE 2005 FEATURES • • • • • • • • • • • • • • DGG OR DGV PACKAGE TOP VIEW Member of the Texas Instruments Widebus

Contextual Info: GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER www.ti.com SCES287D – OCTOBER 1999 – REVISED MAY 2005 FEATURES • • • • • • • • • • • • • • Member of the Texas Instruments Widebus Family UBT™ Transceiver Combines D-Type Latches

GTL431

Contextual Info: ISSUED DATE :2003/05/15 REVISED DATE :2004/11/25C GTL431 Adjustable Shunt Regulator Description The GTL431 series are three-terminal adjustable regulators with guaranteed thermal stability over applicable temperature ranges. The output voltage may be set to any value between VREF approximately 2.495v and 36v with two external resistors.

PAC470R4GQ

Contextual Info: PACR4G CALIFORNIA MICRO DEVICES P/Active High Performance Bus Termination Network Features Applications • Designed especially for High Performance computers/servers • High Performance servers • Provides high speed bus termination • GTL, NTL, ECL terminator

CS5207

Abstract: CS5207-2 IN4002
Contextual Info: CS5207-2 7.0 A, 1.5 V Fixed Linear Regulator The CS5207–2 provides 7.0 A at 1.5 V with an accuracy of ±2.0 %. The regulator is intended for use as an active termination for the GTL bus on Intel based motherboards. The fast loop response and low dropout voltage make these regulators ideal for applications where