GRP SHEET Search Results

Contextual Info: 1000EA Family Architectural Description four outputs, which can be configured to be either combinatorial or registered. Inputs to the GLB come from the Global Routing Pool GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that

Contextual Info: F MADE O ING SETT THERMO RIAL MATE ADVANCE GRP System Switched Interlocked socket outlets ADVANCE GRP System > SWITCHED INTERLOCKED SOCKET OUTLETS > REFERENCE STANDARDS EN 60309-1 Plugs, socket outlets and couplers for industrial purposes. Part 1: general requirements.

AGA NX-19

Abstract: NX-19 modbus totalflow NX19 Exd11B gas Smart meter ABB gas flow meter down hole ISO-5167 gas chromatograph
Contextual Info: Data Sheet 2101199-AD Measurement and Automation Products XSERIES FLOW COMPUTERS XFC and XSERIES REMOTE CONTROLLERS (XRC) Integrated Packages Battery powered Solar Panel or other DC voltage charging system Communications equipment in enclosure CSA C/US Class I, Div 2, Grp CD,

2032VE

Contextual Info: ispLSI 2032VE 3.3V In-System Programmable High Density SuperFAST PLD Functional Block Diagram Global Routing Pool GRP Input Bus • 3.3V LOW VOLTAGE 2032 ARCHITECTURE — Interfaces With Standard 5V TTL Devices • HIGH PERFORMANCE E2CMOS® TECHNOLOGY

2032VE

Abstract: 2032ve110lb
Contextual Info: ispLSI 2032VE 3.3V In-System Programmable High Density SuperFAST PLD Functional Block Diagram Global Routing Pool GRP Input Bus • 3.3V LOW VOLTAGE 2032 ARCHITECTURE — Interfaces With Standard 5V TTL Devices • HIGH PERFORMANCE E2CMOS® TECHNOLOGY

Contextual Info: ispLSI 5384VE In-System Programmable 3.3V SuperWIDE High Density PLD Generic Logic Block Generic Logic Block Input Bus Input Bus Input Bus Input Bus Generic Logic Block Generic Logic Block Input Bus Generic Logic Block Input Bus Global Routing Pool GRP

t16 400

Abstract: 5384VA AF14
Contextual Info: ispLSI 5384V In-System Programmable 3.3V SuperWIDE High Density PLD Generic Logic Block Generic Logic Block Input Bus Input Bus Input Bus Input Bus Generic Logic Block Generic Logic Block Input Bus Generic Logic Block Input Bus Global Routing Pool GRP

2032VE

Abstract: TN48
Contextual Info: ispLSI 2032VE LeadFree Package Options Available! Functional Block Diagram Global Routing Pool GRP Input Bus • 3.3V LOW VOLTAGE 2032 ARCHITECTURE — Interfaces With Standard 5V TTL Devices • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 300 MHz Maximum Operating Frequency

5000VA

Abstract: 5384VE-100LF256 5384VE BGA 256 PACKAGE power dissipation GLB11 TPD16
Contextual Info: ispLSI 5384VE In-System Programmable 3.3V SuperWIDE High Density PLD Generic Logic Block Generic Logic Block Input Bus Input Bus Input Bus Input Bus Generic Logic Block Generic Logic Block Input Bus Generic Logic Block Input Bus Global Routing Pool GRP

2032VE

Contextual Info: ispLSI 2032VE 3.3V In-System Programmable High Density SuperFAST PLD Functional Block Diagram Global Routing Pool GRP Input Bus • 3.3V LOW VOLTAGE 2032 ARCHITECTURE — Interfaces With Standard 5V TTL Devices • HIGH PERFORMANCE E2CMOS® TECHNOLOGY

B208

Abstract: B272 WIN95 fuseselectable EL B17
Contextual Info: ispGDX 160V TM In-System Programmable 3.3V Generic Digital Crosspoint TM Features Functional Block Diagram Global Routing Pool GRP R I/O Cells A IN Boundary Scan Control IM — In-System Programmable — JTAG In-System Programming Interface — Only 3.3V Power Supply Required

2032VE

Contextual Info: ispLSI 2032VE 3.3V In-System Programmable High Density SuperFAST PLD Functional Block Diagram Global Routing Pool GRP Input Bus • 3.3V LOW VOLTAGE 2032 ARCHITECTURE — Interfaces With Standard 5V TTL Devices • HIGH PERFORMANCE E2CMOS® TECHNOLOGY

20004a

Contextual Info: ispLSI 2032VE LeadFree Package Options Available! Functional Block Diagram Global Routing Pool GRP Input Bus • 3.3V LOW VOLTAGE 2032 ARCHITECTURE — Interfaces With Standard 5V TTL Devices • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 300 MHz Maximum Operating Frequency

5000VA

Abstract: 5256VA 5384VA 5512VA 67-Ball bga BGA98
Contextual Info: ispLSI 5384VA In-System Programmable 3.3V SuperWIDE High Density PLD Generic Logic Block Generic Logic Block Input Bus Input Bus Input Bus Input Bus Generic Logic Block Generic Logic Block Input Bus Generic Logic Block Input Bus Global Routing Pool GRP

5000VA

Contextual Info: ispLSI 5384VE In-System Programmable 3.3V SuperWIDE High Density PLD Generic Logic Block Generic Logic Block Input Bus Input Bus Input Bus Input Bus Generic Logic Block Generic Logic Block Input Bus Generic Logic Block Input Bus Global Routing Pool GRP

Contextual Info: 6000 Family Architectural Description available as dedicated device outputs. These signals are also available as inputs to the GRP to facilitate use by onchip logic. ispLSI 6000 Family Introduction The ispLSI 6192 is a high-density, Cell-Based programmable logic device containing a dedicated Memory

Contextual Info: ispLSI 2032VL 2.5V In-System Programmable SuperFAST High Density PLD Functional Block Diagram Global Routing Pool GRP Input Bus Output Routing Pool (ORP) A0 A1 A2 D Q GLB Logic Array A7 A6 D Q D Q A5 D Q A3 Input Bus • SuperFAST HIGH DENSITY IN-SYSTEM

2032VE

Abstract: 2032VL
Contextual Info: ispLSI 2032VL 2.5V In-System Programmable SuperFAST High Density PLD Functional Block Diagram Global Routing Pool GRP Input Bus Output Routing Pool (ORP) A0 A1 A2 D Q GLB Logic Array A7 A6 D Q D Q A5 D Q A3 Input Bus • SuperFAST HIGH DENSITY IN-SYSTEM

2064ve

Abstract: IspLSI 2064VE 2064ve100
Contextual Info: ispLSI 2064VE 3.3V In-System Programmable High Density SuperFAST PLD Features Functional Block Diagram • SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC • • Global Routing Pool GRP Input Bus A0 A1 A2 B5 Logic Array B3 B2 D Q GLB B4 D Q B1 D Q D Q Input Bus

2032VE

Abstract: 2032VL
Contextual Info: ispLSI 2032VL 2.5V In-System Programmable SuperFAST High Density PLD Functional Block Diagram Global Routing Pool GRP Input Bus Output Routing Pool (ORP) A0 A1 A2 D Q GLB Logic Array A7 A6 D Q D Q A5 D Q A3 Input Bus • SuperFAST HIGH DENSITY IN-SYSTEM

6192 c1

Abstract: ispLSI 6192SM grp sheet
Contextual Info: 6000 Family Architectural Description available as dedicated device outputs. These signals are also available as inputs to the GRP to facilitate use by onchip logic. ispLSI 6000 Family Introduction The ispLSI 6192 is a high-density, Cell-Based programmable logic device containing a dedicated Memory

dual port fifo

Contextual Info: 6000 Family Architectural Description available as dedicated device outputs. These signals are also available as inputs to the GRP to facilitate use by onchip logic. ispLSI 6000 Family Introduction The ispLSI 6192 is a high-density, Cell-Based programmable logic device containing a dedicated Memory

Contextual Info: ispLSI 2064V 3.3V High Density Programmable Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC • • Global Routing Pool GRP Input Bus A0 A1 A2 B5 Logic Array B3 B2 D Q GLB B4 D Q B1 D Q D Q Input Bus B6 B7 Output Routing Pool (ORP)

20041A

Abstract: 2064VE 2064VL
Contextual Info: ispLSI 2064VL Features Functional Block Diagram • SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC • • • Input Bus Output Routing Pool ORP Input Bus A1 Logic Array B3 B2 D Q GLB B4 D Q B1 D Q D Q Input Bus Global Routing Pool (GRP) A0 A2 B5 Output Routing Pool (ORP)