GLOBAL CACHE OPERATIONS Search Results

Intel i960 VH Embedded-PCI Processor Provides Integrated Memory Control and PCI Bus Interface

Contextual Info: i960 VH Embedded-PCI Processor Advance Information Datasheet Product Features • High Performance 80960JT Core — Sustained One Instruction/Clock Execution — 16 Kbyte Two-Way Set-Associative Instruction Cache — 4 Kbyte Direct-M apped Data Cache — Sixteen 32-Bit Global Registers

Zilog Z320

Abstract: TDA 120t zilog 3651 a1129 Z80000 Zilog Z80 family RLS07 Z320 Z8000 S7 TDC
Contextual Info: PRELIMINARY P ro d u c t S p e c ific a tio n October 1988 Z320 CPU FEATURES • Full 32-bit architecture and implementation ■ Regular use of operations, addressing modes, and data types in instruction set ■ 4G billion bytes of directly addressable m emory in each

Z280 MPU

Abstract: Z280 Z280 CPU z280cpu z280 input id Z280 MPU input id Z80 CPU Instruction Set Z280MPU
Contextual Info: Product Specification Z280 MPU Microprocessor Unit FEATURES • Designed in CMOS for low power operations. ■ Enhanced Z80 CPU instruction set that maintains object-code compatibility with Z80 microprocessor. ■ Three-stage pipelined, 16-bit CPU architecture with user

zilog Z280

Abstract: Z280 CPU z280 EPU
Contextual Info: ZILOG INC blE; ]> < £ 2 iL G E m c^ fl4[]43 Q 02 S 2 1 S 351 m i l l Product Sp ecificatio n Z280 NPU Microprocessor Unit FEATURES • Designed in CMOS for low power operations. ■ Enhanced Z80 CPU instruction set that maintains object-code compatibility with Z80 microprocessor.

mip 291

Abstract: mip 290
Contextual Info: SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025 – AUGUST 1998 D D D D D D D D D D D D D Single-Chip Parallel Multiple Instruction / Multiple Data MIMD Digital Signal Processor (DSP) More Than Two Billion RISC-Equivalent Operations per Second Master Processor (MP)

MOTION COMPUTING MC C5

Abstract: t32 1-l LC1 D50 11 SGUS025 MIP 289
Contextual Info: SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025 – AUGUST 1998 D D D D D D D D D D D D D Single-Chip Parallel Multiple Instruction / Multiple Data MIMD Digital Signal Processor (DSP) More Than Two Billion RISC-Equivalent Operations per Second Master Processor (MP)

MIP 289

Abstract: LC1 D33 LC1 D38 AB32 AB34 SMJ320C80 mip 291
Contextual Info: SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025 – AUGUST 1998 D D D D D D D D D D D D D Single-Chip Parallel Multiple Instruction / Multiple Data MIMD Digital Signal Processor (DSP) More Than Two Billion RISC-Equivalent Operations per Second Master Processor (MP)

IBM25PPC750L

Abstract: IBM powerpc 750l IBM 750L MPC106 750CXr
Contextual Info: IBM PowerPC 750CXr RISC Microprocessor Errata List DD4.X Version: 1.1 March 7, 2005 Title Page ® Copyright and Disclaimer Copyright International Business Machines Corporation 2001, 2005 All Rights Reserved Printed in the United States of America March 2005

AB32

Abstract: AB34 SM320C80 active aa33
Contextual Info: SM320C80 DIGITAL SIGNAL PROCESSOR SGUS021 – AUGUST 1996 D D D D D D D D D D D D D Single-Chip Parallel Multiple Instruction / Multiple Data MIMD DSP More Than Two Billion RISC-Equivalent Operations per Second Master Processor (MP) – 32-Bit Reduced Instruction Set

mip 291

Abstract: LC1 D33 0x00009f LM 317 ST nth40 0x00008FFF
Contextual Info: SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025A – AUGUST 1998 – REVIISED OCTOBER 2000 D D D D D D D D D D D D D Single-Chip Parallel Multiple Instruction / Multiple Data MIMD Digital Signal Processor (DSP) More Than Two Billion RISC-Equivalent Operations per Second

GK21-0263-00

Abstract: PPC750 IBM PPC750 PowerPC 740 reference manual IBM043641WLA ibm sram
Contextual Info: PowerPC Applications Note PowerPC 750 Design Guidelines Introduction • Chip selects: The 750 L2CE is connected to the global chip select SS. To assist in creating the best system designs using the fastest PowerPC 750s, the following guidelines are recommended.

LC1 D38

Abstract: MIP 289 LC1 D25 004 LC1 D50 AB32 AB34 SM320C80 A1341
Contextual Info: SM320C80 DIGITAL SIGNAL PROCESSOR SGUS021 – AUGUST 1996 D D D D D D D D D D D D D Single-Chip Parallel Multiple Instruction / Multiple Data MIMD DSP More Than Two Billion RISC-Equivalent Operations per Second Master Processor (MP) – 32-Bit Reduced Instruction Set

Contextual Info: TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 — APRIL 1998 • • • • • GGP PACKAGE BOTTOM VIEW Single Chip Parallel MIMD DSP Over 1.5 Billion RISC-like Operations per Second Master Processor (MP) − 32-Bit RISC Processor − IEEE-754 Floating Point

LC1 D25 10

Abstract: TMS320C80 LC1 D63 C8050 1994 AND sdram AND LC1 D38 AB32 AB34 0x0000B000 MP-124
Contextual Info: TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023A – JULY 1994 – REVISED MARCH 1996 D D D D D D Single-Chip Parallel Multiple Instruction / Multiple Data MIMD DSP More Than Two Billion RISC-Equivalent Operations per Second Master Processor (MP) – 32-Bit Reduced Instruction Set

C82 diode

Abstract: AD27 AD29 AD30 TMS320C82
Contextual Info: TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 — APRIL 1998 • • • • • GGP PACKAGE BOTTOM VIEW Single Chip Parallel MIMD DSP Over 1.5 Billion RISC-like Operations per Second Master Processor (MP) − 32-Bit RISC Processor − IEEE-754 Floating Point

Contextual Info: TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 — APRIL 1998 • • • • • GGP PACKAGE BOTTOM VIEW Single Chip Parallel MIMD DSP Over 1.5 Billion RISC-like Operations per Second Master Processor (MP) − 32-Bit RISC Processor − IEEE-754 Floating Point

CY7C1335

Abstract: CY7C1336
Contextual Info: CY7C1335 CY7C1336 ADVANCED INFORMATION 32K x 32 Synchronous Cache RAM D D D Features D Supports 75ĆMHz Pentiumt and PowerPCt operations with zero wait states D Fully registers inputs and outputs for pipelined operation D D D 32K x 32 common I/O architecture

CY7C1335

Abstract: CY7C1336
Contextual Info: CY7C1335 CY7C1336 ADVANCED INFORMATION 32K x 32 Synchronous Cache RAM D D D Features D Supports 75ĆMHz Pentiumt and PowerPCt operations with zero wait states D Fully registers inputs and outputs for pipelined operation D D D 32K x 32 common I/O architecture

C82 diode

Abstract: AD27 AD29 AD30 TMS320C82 RCA11
Contextual Info: TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 — APRIL 1998 • • • • • GGP PACKAGE BOTTOM VIEW Single Chip Parallel MIMD DSP Over 1.5 Billion RISC-like Operations per Second Master Processor (MP) − 32-Bit RISC Processor − IEEE-754 Floating Point

Contextual Info: SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B - AUGUST 1998 - REVISED JUNE 2002 D Single-Chip Parallel Multiple D D D D D D D D D D D D Instruction/Multiple Data MIMD Digital Signal Processor (DSP) More Than Two Billion RISC-Equivalent Operations per Second

Contextual Info: SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B - AUGUST 1998 - REVISED JUNE 2002 D Single-Chip Parallel Multiple D D D D D D D D D D D D Instruction/Multiple Data MIMD Digital Signal Processor (DSP) More Than Two Billion RISC-Equivalent Operations per Second

Contextual Info: SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B - AUGUST 1998 - REVISED JUNE 2002 D Single-Chip Parallel Multiple D D D D D D D D D D D D Instruction/Multiple Data MIMD Digital Signal Processor (DSP) More Than Two Billion RISC-Equivalent Operations per Second

MX 232

Abstract: mip 291
Contextual Info: SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B - AUGUST 1998 - REVISED JUNE 2002 D Single-Chip Parallel Multiple D D D D D D D D D D D D Instruction/Multiple Data MIMD Digital Signal Processor (DSP) More Than Two Billion RISC-Equivalent Operations per Second

Contextual Info: SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B - AUGUST 1998 - REVISED JUNE 2002 D Single-Chip Parallel Multiple D D D D D D D D D D D D Instruction/Multiple Data MIMD Digital Signal Processor (DSP) More Than Two Billion RISC-Equivalent Operations per Second