GCK 164 Search Results

XC95288

Abstract: BG352 HQ208 XC9500
Contextual Info:  XC95288 In-System Programmable CPLD January, 1997 Version 1.0 Advanced Product Specification Features Description • 10 ns pin-to-pin logic delays on all pins • fCNT to 111 MHz • 288 macrocells with 6,400 usable gates • Up to 192 user I/O pins

PQ160

Abstract: XC9500 XC95216
Contextual Info:  XC95216 In-System Programmable CPLD March, 1997 Version 1.1 Product Specification Features Power Management • 10 ns pin-to-pin logic delays on all pins • fCNT to 111 MHz • 216 macrocells with 4800 usable gates • Up to 166 user I/O pins • 5 V in-system programmable

XC95288

Abstract: BG352 HQ208 XC9500 X5906 X7131 HQ208I
Contextual Info: 1 XC95288 In-System Programmable CPLD  December 4, 1998 Version 3.0 1 1* Product Specification Features Power Management • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 192 user I/O pins

A23 780-4

Abstract: 471 E25 BG352 HQ208 XC9500 XC95288
Contextual Info: XC95288 In-System Programmable CPLD  November 12, 1997 Version 2.0 3* Preliminary Product Specification Features MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f • • • • • Where: • • • • • • • • • • • MCHP = Macrocells in high-performance mode

HQ208

Abstract: PQ160 XC95216
Contextual Info:  XC95216 In-System Programmable CPLD August 1, 1996 Version 1.1 Preliminary Product Specification Features Power Management • • • • • Power dissipation can be reduced in the XC95216 by configuring macrocells to standard or low-power modes of

471 E25

Abstract: PQ160 XC9500 XC95216
Contextual Info: XC95216 In-System Programmable CPLD  October 28, 1997 Version 2.0 3* Product Specification Features Power Management • • • • • Power dissipation can be reduced in the XC95216 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize

471 E25

Abstract: XC95216 Family 134-174 PQ160 XC9500 XC95216
Contextual Info: 1 XC95216 In-System Programmable CPLD  August 21, 2001 Version 3.1 1 0* Product Specification Features Power Management • • 10 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 216 macrocells with 4800 usable gates Up to 166 user I/O pins

XC95288

Abstract: PQ208 TQ144 XC9500XL XC95288XL 208pin footprint pqfp 208
Contextual Info:  XC95288XL High Performance CPLD September 28, 1998 Version 1.0 Advance Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output

471 E25

Abstract: XC95216-20PQ160I DS06 HQ208 PQ160 XC9500 XC95216 XC95216-10HQ208I XC95216-10PQ160 n439
Contextual Info: XC95216 In-System Programmable CPLD R DS068 v4.1 August 21, 2003 5 Product Specification Features Description • • 10 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 216 macrocells with 4,800 usable gates Up to 166 user I/O pins 5V in-system programmable

PQ160

Abstract: XC9500 XC95216
Contextual Info: 1 XC95216 In-System Programmable CPLD  August 21, 2001 Version 3.1 1 0* Product Specification Features Power Management • • 10 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 216 macrocells with 4800 usable gates Up to 166 user I/O pins

XC95288

Abstract: BG352 HQ208 XC9500 n439
Contextual Info: XC95288 In-System Programmable CPLD R DS069 v4.1 August 21, 2003 5 Product Specification Features Description • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 166 user I/O pins 5V in-system programmable

XC95288-15HQ208I

Abstract: XC95288
Contextual Info: Product Obsolete/Under Obsolescence XC95288 In-System Programmable CPLD R DS069 v5.0 May 17, 2013 5 Product Specification Features Description • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates

Contextual Info: flXIUNX XC95216 In-System Programmable CPLD December 4, 1998 Version 3.0 Product Specification Features Power Management • 10 ns pin-to-pin logic delays on all pins • fcN T to 111 MHz • • • 216 macrocells with 4800 usable gates Up to 166 user I/O pins

XC95288

Contextual Info: flXIU N X XC95286 In-System Programmable CPLD October 28, 1997 Version 2.0 Preliminary Product Specification Features MC h p (1.7) + MC lp (0.9) + MC (0.006 m A/M Hz) f • 15 ns pin-to-pin logic delays on all pins Where: • • • • fcNT to MHz 288 macrocells with 6,400 usable gates

XC95288

Contextual Info: flXIUNX XC95288 In-System Programmable CPLD December 4, 1998 Version 3.0 Product Specification Features Power Management • • 15 ns pin-to-pin logic delays on all pins fcN T 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 192 user I/O pins

XC95216-20PQG160I

Abstract: XC95216-15PQ160I 471 E25 XC95216 Family XC95216-10PQ160C XC95216-10PQ160I XC95216-15PQG160C XC95216-15PQG160I XC95216-10PQG160I XC9500
Contextual Info: XC95216 In-System Programmable CPLD R 5 Note: The 352-pin BGA packages are being discontinued for XC95216 devices. You cannot order these packages after May 14, 2008. Xilinx recommends replacing XC95216 in 352-pin BGA packages with XC95288 devices in 352-pin BGA packages in all designs as soon as possible. Recommended replacements are pin compatible, but

R1019

Contextual Info: C13 C15 C20 C22 C25 C26 C42 C43 SDO CSB SCLK SDIO OVDD pin36 OVDD pin27 OVDD D C14 0.1uF C45 C44 pin56 pin70 OUTFMT pin23 nap_sleep_normal pin22 output_mode pin16 clkdivn pin15 Vcm pin71 AVDD pin24 AVDD pin19 AVDD pin12 AVDD pin6 AVDD pin1 AVDD D C12 C24 0.1uF

TQ144

Abstract: XC9500XV XC95288XV XC95288XV-10 XC95288XV-5 XC95288XV-7 csp192 T9423 w7510
Contextual Info: XC95288XV High-Performance CPLD R DS050 v2.2 August 27, 2001 5 Advance Product Specification Features Power Estimation • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell

T9423

Abstract: TQ144 XC9500XL XC95288 XC95288XL W-7510 w7510 k1739
Contextual Info: XC95288XL High Performance CPLD DS055 v1.4 March 19, 2001 5 Features • • • • • • • • • • • 6 ns pin-to-pin logic delays System frequency up to 208 MHz 288 macrocells with 6,400 usable gates Available in small footprint packages - 144-pin TQFP (117 user I/O pins)

v19 423

Abstract: V19 312 TQ144 XC9500XL XC95288 XC95288XL w17 88
Contextual Info: 1 XC95288XL High Performance CPLD R June 7, 1999 Version 1.2 5* Preliminary Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output

780 AC

Contextual Info: £ XILINX XC95288XL High Performance CPLD February 5, 1999 Version 1.1 Advance Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depend­ ing on the system frequency, design application and output

Contextual Info: XC95288XL High Performance CPLD DS055 v1.6 May 27, 2003 5 Features • • • • • • • • • • • 6 ns pin-to-pin logic delays System frequency up to 208 MHz 288 macrocells with 6,400 usable gates Available in small footprint packages - 144-pin TQFP (117 user I/O pins)

D12N

Abstract: ADT1-1WT d9n diode NB6L14 SDA 5512 108 c42 KDC5512-50EVAL D13N D13N TECHNICAL DATA 5514P
Contextual Info: KDC5512EVAL, KDC5512HEVAL, KDC5512-50EVAL, KDC5514EVAL C10 100pF SDO C38 C37 100pF CSB SCLK 100pF SDIO 100pF C36 100pF C35 OVDD pin36 OVDD C27 0.1uF pin27 C24 0.1uF pin56 C14 0.1uF OVDD 6 7 8 AVDD GND GND C11 100pF 9 10 VinIm VinIp GND AVDD OVDD DGND 56 55

Contextual Info: 1 1 ISLA216IR72EV1Z 1 ADC Input FS - Neglects 3-4dB Input Network Loss 19 20 21 AVDD K=15uV R=49.9K OVDD DGND lvds_2 lvds_n2 lvds_3 lvds_n3 lvds_4 lvds_n4 62 61 60 59 58 57 56 55 OVDD OVSS DGND lvds_1 lvds_n1 64 63 D0P D0N D1P D1N D2P D2N 48 47 CSB SCLK C37