GCK 164 Search Results

AO211

Abstract: STD130 SAMSUNG 834
Contextual Info: Appendix Maximum Fanouts C Maximum Fanouts of Internal Macrocells Maximum Fanouts of Internal Macrocells When input tR/tF = 0.155ns, one fanout (SL = 0.00517pF, wire load = 0.048pF, 0.048pF is correspondent with 300µm wire) Cell Name ad2 ad2b ad2bd2 ad2bd4

GCK 164

Abstract: samsung 649 ao21 OA21D
Contextual Info: Appendix Maximum Fanouts C Maximum Fanouts of Internal Macrocells Maximum Fanouts of Internal Macrocells When input tR/tF = 0.204ns, one fanout (SL = 0.00486pF, wire load = 0.048pF, 0.048pF is correspondent with 300µm wire) Cell Name ad2_lp ad2b_lp ad2bd2_lp

XC95288

Abstract: BG352 HQ208 XC9500
Contextual Info:  XC95288 In-System Programmable CPLD January, 1997 Version 1.0 Advanced Product Specification Features Description • 10 ns pin-to-pin logic delays on all pins • fCNT to 111 MHz • 288 macrocells with 6,400 usable gates • Up to 192 user I/O pins

PQ160

Abstract: XC9500 XC95216
Contextual Info:  XC95216 In-System Programmable CPLD March, 1997 Version 1.1 Product Specification Features Power Management • 10 ns pin-to-pin logic delays on all pins • fCNT to 111 MHz • 216 macrocells with 4800 usable gates • Up to 166 user I/O pins • 5 V in-system programmable

Contextual Info: tlXIUNX* XC95288 In-System Programmable CPLD J a n u a ry , 1 9 9 7 V e rs io n 1.0 Advanced Product Specification Features Description • 10 ns pin-to-pin logic delays on all pins • ^CNT to 111 MHz • • • 288 m acrocells with 6,400 usable gates

cd rom 40 pin interface

Abstract: CL680 C-Cube C-Cube microsystems
Contextual Info: Table of Contents Section I. General Information 1 Introduction 1.1 1.2 Overview New Features 1.2.1 Audio 1.2.2 Video 1.2.3 Integration 1.3 Core Features 1.3.1 Flexible Video Interface with High-quality Video Output 1.3.2 Antialiased Video Overlays 1.3.3 Low voltage, Low Power Operation in Small Package

471 E25

Abstract: PQ160 XC9500 XC95216
Contextual Info: 1 XC95216 In-System Programmable CPLD  December 4, 1998 Version 3.0 1 12* Product Specification Features Power Management • • 10 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 216 macrocells with 4800 usable gates Up to 166 user I/O pins

XC95216

Contextual Info: EXILINX XC95216 In-System Programmable CPLD October 28, 1997 Version 2.0 Product Specification Features Power Management • • 10 ns pin-to-pin logic delays on all pins fQNT to 111 MHz • • • 216 macrocells with 4800 usable gates Up to 166 user I/O pins

XC95288

Abstract: BG352 HQ208 XC9500 X5906 X7131 HQ208I
Contextual Info: 1 XC95288 In-System Programmable CPLD  December 4, 1998 Version 3.0 1 1* Product Specification Features Power Management • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 192 user I/O pins

AC1284

Contextual Info: KXILINX XC95288 In-System Programmable CPLD April, 1997 Version 1.0 Preliminary Product Specification Features Description • 15 ns pin-to-pin logic delays on all pins • • • • fcNT t ° MHz 288 macrocells with 6,400 usable gates Up to 192 user I/O pins

A23 780-4

Abstract: 471 E25 BG352 HQ208 XC9500 XC95288
Contextual Info: XC95288 In-System Programmable CPLD  November 12, 1997 Version 2.0 3* Preliminary Product Specification Features MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f • • • • • Where: • • • • • • • • • • • MCHP = Macrocells in high-performance mode

HQ208

Abstract: PQ160 XC95216
Contextual Info:  XC95216 In-System Programmable CPLD August 1, 1996 Version 1.1 Preliminary Product Specification Features Power Management • • • • • Power dissipation can be reduced in the XC95216 by configuring macrocells to standard or low-power modes of

471 E25

Abstract: PQ160 XC9500 XC95216
Contextual Info: XC95216 In-System Programmable CPLD  October 28, 1997 Version 2.0 3* Product Specification Features Power Management • • • • • Power dissipation can be reduced in the XC95216 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize

471 E25

Abstract: XC95216 Family 134-174 PQ160 XC9500 XC95216
Contextual Info: 1 XC95216 In-System Programmable CPLD  August 21, 2001 Version 3.1 1 0* Product Specification Features Power Management • • 10 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 216 macrocells with 4800 usable gates Up to 166 user I/O pins

10HQ

Abstract: XC95288 471 E25 HQ208 XC9500
Contextual Info: XC95288 In-System Programmable CPLD  September 15, 1999 Version 4.0 5* Product Specification Features Power Management • • 10 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 192 user I/O pins

t20m19

Contextual Info: XC95288XL High Performance CPLD R February 5, 1999 Version 1.1 1* Advance Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell

XC95216

Abstract: XC95216-10PQ160I
Contextual Info: XC95216 In-System Programmable CPLD R DS068 v4.0 June 18, 2003 5 Product Specification Features Description • • 10 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 216 macrocells with 4,800 usable gates Up to 166 user I/O pins 5V in-system programmable

Contextual Info: flX IU N X XC95216 In-System Programmable CPLD October 28, 1997 Version 2.0 Product Specification Features Power Management • 10 ns pin-to-pin logic delays on all pins • fcNT to 111 MHz • • • 216 macrocells with 4800 usable gates Up to 166 user I/O pins

xc95216

Abstract: 352-BALL
Contextual Info: XC95216 In-System Programmable CPLD R DS068 v4.2 April 15, 2005 5 Product Specification Features Description • • 10 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 216 macrocells with 4,800 usable gates Up to 166 user I/O pins 5V in-system programmable

xc95288

Abstract: BG352 XC95288-20HQ208C XC95288-20HQ208
Contextual Info: XC95288 In-System Programmable CPLD R DS069 v4.0 June 18, 2003 5 Product Specification Features Description • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 166 user I/O pins 5V in-system programmable

471 E25

Abstract: XC95216-20PQ160I DS06 HQ208 PQ160 XC9500 XC95216 XC95216-10HQ208I XC95216-10PQ160 n439
Contextual Info: XC95216 In-System Programmable CPLD R DS068 v4.1 August 21, 2003 5 Product Specification Features Description • • 10 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 216 macrocells with 4,800 usable gates Up to 166 user I/O pins 5V in-system programmable

PQ160

Abstract: XC9500 XC95216
Contextual Info: 1 XC95216 In-System Programmable CPLD  August 21, 2001 Version 3.1 1 0* Product Specification Features Power Management • • 10 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 216 macrocells with 4800 usable gates Up to 166 user I/O pins

XC95288

Abstract: BG352 HQ208 XC9500 n439
Contextual Info: XC95288 In-System Programmable CPLD R DS069 v4.1 August 21, 2003 5 Product Specification Features Description • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 166 user I/O pins 5V in-system programmable

XC95288

Abstract: Marking af1 AF24 marking
Contextual Info: XC95288 In-System Programmable CPLD R DS069 v4.2 April 15, 2005 5 Product Specification Features Description • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 166 user I/O pins 5V in-system programmable