FLIP FLOP COUNTER Search Results

DM74ALS174N

Abstract: 74ALS175 DM74ALS174 DM74ALS174M DM74ALS174SJ DM74ALS175 DM74ALS175M M16A M16D N16A
Contextual Info: DM74ALS174 DM74ALS175 Hex Quad D Flip-Flop with Clear General Description Features These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic Both have an asynchronous clear input and the quad 175 version features complementary outputs from each flip-flop

MM74C74N

Abstract: AN-90 M14A MM74C74 MM74C74M MS-001 N14A
Contextual Info: Revised January 1999 MM74C74 Dual D-Type Flip-Flop General Description • High noise immunity: The MM74C74 dual D-type flip-flop is a monolithic complementary MOS CMOS integrated circuit constructed with N- and P-channel enhancement transistors. Each flip-flop

C1995

Abstract: DM74ALS DM74ALS109A DM74ALS109AM DM74ALS109AN LS109 M16A N16A
Contextual Info: DM74ALS109A Dual J-K PositiveEdge-Triggered Flip-Flop with Preset and Clear General Description Features The DM54ALS109A is a dual edge-triggered flip-flop Each flip-flop has individual J K clock clear and preset inputs and also complementary Q and Q outputs

CI 74C

Abstract: AN-90 MM54C74 MM74C74 MM54C74J
Contextual Info: February 1988 MM54C74/MM74C74 Dual D Flip-Flop General Description The MM54C74/MM74C74 dual D flip-flop is a monolithic complementary MOS CMOS integrated circuit constructed with N- and P-channel enhancement transistors. Each flip­ flop has independent data, preset, clear and clock inputs

COMPLEMENTA

Abstract: cd4013bm
Contextual Info: CD4013BM/CD4013BC National ÆjÉ Semiconductor CD4013BM/CD4013BC Dual D Flip-Flop General Description Features The CD4013B dual D flip-flop is a monolithic complementa­ ry MOS CMOS integrated circuit constructed with N- and P-channel enhancement mode transistors. Each flip-flop

DM74ALS

Abstract: DM74ALS109A DM74ALS109AM DM74ALS109AN LS109 M16A N16A DM74ALS109
Contextual Info: DM74ALS109A Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and Clear General Description Features The DM54ALS109A is a dual edge-triggered flip-flop. Each flip-flop has individual J, K, clock, clear and preset inputs, and also complementary Q and Q outputs.

Contextual Info: m jé National Semiconductor DM74AS109 Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and Clear General Description Features The ’AS109 is a dual edge-triggered flip-flop. Each flip-flop has individual J, K, clock, clear and preset inputs, and also

CD4013BC

Abstract: CD4013BCM CD4013BCN specifications CD4013BCN 74LS CD4013B CD4013BCSJ M14A M14D N14A
Contextual Info: CD4013BC Dual D-Type Flip-Flop October 1987 Revised March 2002 CD4013BC Dual D-Type Flip-Flop General Description Features The CD4013B dual D-type flip-flop is a monolithic complementary MOS CMOS integrated circuit constructed with N- and P-channel enhancement mode transistors. Each

DM74ALS109A

Abstract: DM74ALS109AM DM74ALS109AN LS109 M16A MS-001 N16E
Contextual Info: Revised February 2000 DM74ALS109A Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and Clear General Description Features The DM74ALS109A is a dual edge-triggered flip-flop. Each flip-flop has individual J, K, clock, clear and preset inputs, and also complementary Q and Q outputs.

Contextual Info: December 1989 Semiconductor DM74ALS109A Dual J-K PositiveEdge-Triggered Flip-Flop with Preset and Clear General Description Features The DM54ALS109A is a dual edge-triggered flip-flop. Each flip-flop has individual J, K, clock, clear and preset inputs, and also complementary Q and Q outputs.

Contextual Info: 109 A National Semiconductor DM74ALS109A Dual J-K PositiveEdge-Triggered Flip-Flop with Preset and Clear General Description Features The DM54ALS109A is a dual edge-triggered flip-flop. Each flip-flop has individual J, K, clock, clear and preset inputs, and also complementary Q and Q outputs.

CD4013BCN specifications

Abstract: 74LS CD4013B CD4013BC CD4013BCM CD4013BCN CD4013BCSJ M14A M14D N14A
Contextual Info: Revised January 1999 CD4013BC Dual D-Type Flip-Flop General Description Features The CD4013B dual D-type flip-flop is a monolithic complementary MOS CMOS integrated circuit constructed with N- and P-channel enhancement mode transistors. Each flip-flop has independent data, set, reset, and clock inputs

CD4013B

Abstract: CD4013BC 74LS C1995 CD4013BCJ CD4013BM CD4013BMJ CD4013BMN J14A B11b3
Contextual Info: CD4013BM CD4013BC Dual D Flip-Flop General Description Features The CD4013B dual D flip-flop is a monolithic complementary MOS CMOS integrated circuit constructed with N- and P-channel enhancement mode transistors Each flip-flop has independent data set reset and clock inputs and ‘‘Q’’

cd4013bcn

Abstract: CD4013BM 74LS C1995 CD4013B CD4013BC CD4013BCJ CD4013BMJ CD4013BMN J14A
Contextual Info: CD4013BM CD4013BC Dual D Flip-Flop General Description Features The CD4013B dual D flip-flop is a monolithic complementary MOS CMOS integrated circuit constructed with N- and P-channel enhancement mode transistors Each flip-flop has independent data set reset and clock inputs and ‘‘Q’’

MC100EL35

Abstract: k 3555 HEL35 KL35 MC10EL35
Contextual Info: MC10EL35, MC100EL35 5V ECL JK Flip-Flop Description The MC10EL/100EL35 is a high speed JK flip-flop. The J/K data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition

MM74C74N

Abstract: AN-90 M14A MM74C74 MM74C74M MS-001 N14A
Contextual Info: Revised May 2002 MM74C74 Dual D-Type Flip-Flop General Description Features The MM74C74 dual D-type flip-flop is a monolithic complementary MOS CMOS integrated circuit constructed with N- and P-channel enhancement transistors. Each flip-flop has independent data, preset, clear and clock inputs and Q

HEL35

Abstract: MC100EL35 KL35 MC10EL35 KEL35 transistor k 4110
Contextual Info: MC10EL35, MC100EL35 5V ECL JK Flip-Flop Description The MC10EL/100EL35 is a high speed JK flip-flop. The J/K data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition

Contextual Info: February 1988 CD4013BM/CD4013BC Dual D Flip-Flop General Description Features The CD4013B dual D flip-flop is a monolithic complementa­ ry MOS CMOS integrated circuit constructed with N- and P-channel enhancement mode transistors. Each flip-flop has independent data, set, reset, and clock inputs and “ Q ”

40CMOS

Contextual Info: MM54C74,MM74C74 MM54C74 MM74C74 Dual D Flip-Flop Literature Number: SNOS336A MM54C74 MM74C74 Dual D Flip-Flop General Description The MM54C74 MM74C74 dual D flip-flop is a monolithic complementary MOS CMOS integrated circuit constructed with N- and P-channel enhancement transistors Each flipflop has independent data preset clear and clock inputs

5958

Abstract: 74LS AN-90 C1995 CD4027B CD4027BC CD4027BCJ CD4027BM CD4027BMJ J16A
Contextual Info: CD4027BM CD4027BC Dual J-K Master Slave Flip-Flop with Set and Reset General Description Features These dual J-K flip-flops are monolithic complementary MOS CMOS integrated circuits constructed with N- and Pchannel enhancement mode transistors Each flip-flop has

DM54ALS174J

Abstract: DM54ALS175J 54ALS175 54als174
Contextual Info: National Juâ Semiconductor DM54ALS174/DM54ALS175/DM74ALS174/DM74ALS175 Hex/Quad D Flip-Flop with Clear General Description Features These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. Both have an asynchro­

ALS74A

Abstract: DM74ALS74AN DM74ALS74A DM74ALS74AM DM74ALS74ASJ LS74 M14A M14D N14A dm74als74am fairchild
Contextual Info: DM74ALS74A Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear General Description Features The ’ALS74A contains two independent positive edge-triggered flip-flops. Each flip-flop has individual D, clock, clear and preset inputs, and also complementary Q

MC100E131

Abstract: MC100E131FN MC100E131FNR2 MC10E131 MC10E131FN MC10E131FNR2
Contextual Info: MC10E131, MC100E131 5V ECL 4-Bit D Flip-Flop The MC10E/100E131 is a quad master-slave D-type flip-flop with differential outputs. Each flip-flop may be clocked separately by holding Common Clock CC LOW and using the Clock Enable (CE) inputs for clocking. Common clocking is achieved by holding the CE

Contextual Info: MC10E131, MC100E131 5V ECL 4-Bit D Flip-Flop Description The MC10E/100E131 is a quad master-slave D-type flip-flop with differential outputs. Each flip-flop may be clocked separately by holding Common Clock CC LOW and using the Clock Enable (CE) inputs for clocking. Common clocking is achieved by holding the CE