FILTER FP1P Search Results
FILTER FP1P Result Highlights (5)
| Part | ECAD Model | Manufacturer | Description | Download | Buy |
|---|---|---|---|---|---|
| FCE17E09PC45B | Amphenol Communications Solutions | FILTERED D-SUB FCE17 SERIES | |||
| FCE17E09SC350G | Amphenol Communications Solutions | FILTERED D-SUB FCE17 SERIES | |||
| FCE17E09PC350G | Amphenol Communications Solutions | FILTERED D-SUB FCE17 SERIES | |||
| FCE17B25PC350G | Amphenol Communications Solutions | FILTERED D-SUB FCE17 SERIES | |||
| FCE17A15PC350G | Amphenol Communications Solutions | FILTERED D-SUB FCE17 SERIES |
FILTER FP1P Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
GR-1244-CORE
Abstract: MS-026 ZL50011
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zl50011512-chsti0-15gr-1244-core+1 | |
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Contextual Info: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features • September 2011 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation Ordering Information ZL50011/GDC 144 Ball LBGA Trays ZL50011QCG1 160 Pin LQFP* Trays, Bake & Drypack |
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zl50011zl50011/gdczl50011qcg1zl50011gdg2+1 | |
GR-1244-CORE
Abstract: MS-026 ZL50011
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Original |
zl50011gr-1244-corems-026 | |
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Contextual Info: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features July 2005 • 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Integrated Digital Phase-Locked Loop DPLL |
Original |
zl50011gr-1244-core | |
ZL50011QCG1
Abstract: GR-1244-CORE MS-026 ZL50011
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Original |
zl50011zl50011/qcczl50011/gdczl50011qcg1+3 | |
GR-1244-CORE
Abstract: MS-026 ZL50011 11CH marking
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Original |
zl50011gr-1244-corems-02611ch marking | |
32.768Mhz oscillator
Abstract: FOX 20.000 MHZ GR-1244-CORE MS-026 ZL50011 tfk8
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Original |
zl50011gr-1244-core32.768mhz oscillatorfox 20.000 mhz+2 | |
filter FP1PContextual Info: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD Per-stream output channel and output bit delay programming with fractional bit advancement Multiple frame pulse outputs and reference clock outputs Per-channel constant throughput delay |
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zl50010gr-1244-corefilter fp1p | |
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Contextual Info: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD • • • • • • • • • RESET Data Memory P/S Converter Output HiZ Control Connection Memory Microprocessor Interface and DPLL OSC Output Timing STo0-15 STOHZ0-15 FPo0 CKo0 |
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zl50010sti0-15zl50010/gdczl50010qcg1+1 | |
GR-1244-CORE
Abstract: MS-026 ZL50010
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zl50010sti0-15zl50010/qcczl50010/gdc+3 | |
ZL50010QCG1
Abstract: GR-1244-CORE MS-026 ZL50010 32CH1
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zl50010sti0-15zl50010/qcczl50010/gdc+5 | |
GR-1244-CORE
Abstract: MS-026 ZL50010 TFPW0
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zl50010sti0-15zl50010/qcczl50010/gdc+4 | |
FOX 20.000 MHZ
Abstract: LMT 324 slv ca2 GR-1244-CORE MS-026 ZL50010 STO14 tfk8k
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zl50010sti0-15zl50010/qcczl50010/gdc+8 | |
ZL50010
Abstract: TFR1M GR-1244-CORE MS-026
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zl50010512-chsti0-15zl50010/qcc+5 | |
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