FIFO FLAG READ WRITE EMPTY FULL BUFFER CASCADE ER Search Results

PLD12

Abstract: 74LS429 N74LS429N PLD11 1N814 "FRC"
Contextual Info: 74LS429 FIFO RAM Controller FRC Preliminary Specification Logic Products FEATURES • Direct addressing up to 64K • Cascadable for addressing beyond 64K • Asynchronous Read/Write operation • 3-State address outputs • Selectable FIFO length in multiples of 2

Contextual Info: LF3312 12-Mbit Frame Buffer / FIFO DEVICES INCORPORATED Advance Information FEATURES 12,441,600-bit Frame Memory May be Organized Into the Following Configurations: • 1,555,200 x 8-bit single channel • 1,244,160 x 10-bit (single channel) • 1,036,800 x 12-bit (single channel)

lathes

Abstract: LF3312 3312
Contextual Info: LF3312 12-Mbit Frame Buffer / FIFO DEVICES INCORPORATED Advance Information FEATURES 12,441,600-bit Frame Memory May be Organized Into the Following Configurations: • 1,555,200 x 8-bit single channel • 1,244,160 x 10-bit (single channel) • 1,036,800 x 12-bit (single channel)

Contextual Info: LF3312 12-Mbit Frame Buffer / FIFO DEVICES INCORPORATED Advance Information FEATURES 12,441,600-bit Frame Memory May be Organized Into the Following Configurations: • 1,555,200 x 8-bit single channel • 1,244,160 x 10-bit (single channel) • 1,036,800 x 12-bit (single channel)

syn 7580

Abstract: 80960CA intel 8212 data sheet BSDE diode marking code 4n TPS 1028 1840H bicon TTL catalog Bt8215EPF
Contextual Info: Bt8215 Bidirectional Cell Buffer The Bt8215 Bidirectional Cell Buffer simplifies full-duplex communication between a 32-bit wide system bus and a 8-bit duplex peripheral bus. The buffer depth in each direction is 2048 bytes and can easily be expanded with off-theshelf FIFO parts. Special modes for buffering ATM cells are included.

74LS429

Contextual Info: 74LS429 FIFO RAM Controller FRC Preliminary Specification Logic Products FEATURES • Direct addressing up to 64K • Cascadable for addressing beyond 64K • Asynchronous Read/Write operation • 3-State address outputs • Selectable FIFO length in multiples of 2

74LS429

Abstract: PLD2 N74LS429N
Contextual Info: Signetics 74LS429 FIFO RAM Controller FRC Preliminary Specification Logic Products FEATURES • Direct addressing up to 64K • Cascadable for addressing beyond 64K • Asynchronous Read/Write operation • 3-State address outputs • Selectable FIFO length in

LF3312

Abstract: 3312 LDS-3312
Contextual Info: LF3312 12-Mbit Frame Buffer / FIFO DEVICES INCORPORATED Advance Information Features 12,441,600-bit Frame Memory May be Organized Into the Following Configurations: • 1,555,200 x 8-bit single channel • 1,244,160 x 10-bit (single channel) • 1,036,800 x 12-bit (single channel)

MARKING IAF

Contextual Info: 1 .0 Product Description 1.1 Overview The Bt8215 is a bidirectional buffer with a 36-bit bidirectional port and 9-bit uni­ directional ports that can be configured to transfer fixed-length cells. Each direc­ tion can store up to 512 36-bit words. This part, therefore, replaces eight

CY7B923

Abstract: C2752
Contextual Info: PRELIMINARY CY7B929DX HOTLink-II Transceiver functionality, integration, and faster data rates, over the field proven CY7B923/933 HOTLink. Functional Description Framer Deserializer Control Figure 1. HOTLink-II System Connections HOTLink and HOTLink II are trademarks of Cypress Semiconductor Corporation.

RJH 32

Contextual Info: 512 x 18/1024 x 18 Synchronous FIFO FEATURES • May be Cascaded for Increased Depth, or Paralleled for Increased Width • Fast Cycle Times: 20/25/35 ns • 16-mA-l<x Three-State Outputs • Pin-Compatible Drop-In Replacements for IDT72215B/25B FIFOs • Choice of IDT-Compatible or Enhanced Operating

7C408A

Contextual Info: CY7C408A CY7C409A m w C Y PR ESS Features • 64 x 8 and 64 x 9 first-in first-out FIFO buffer memory • 35-MHz shift in and shift out rates • Almost Full/Almost Empty and Half Full flags • Dual-port RAM architecture • Fast (50-ns) bubble-through

25bco

Abstract: LH540215 LH540225 GAL20ra10
Contextual Info: LH540215/25 512 x 18 / 1024 × 18 Synchronous FIFO • May be Cascaded for Increased Depth, or FEATURES Paralleled for Increased Width • Fast Cycle Times: 20/25/35 ns • Pin-Compatible Drop-In Replacements for • 16-mA-IOL Three-State Outputs • Five Status Flags: Full, Almost-Full, Half-Full,

68-PIN

Abstract: LH540215 LH540225 D1591
Contextual Info: LH540215/25 512 x 18 / 1024 × 18 Synchronous FIFO • May be Cascaded for Increased Depth, or FEATURES Paralleled for Increased Width • Fast Cycle Times: 20/25/35 ns • Pin-Compatible Drop-In Replacements for • Five Status Flags: Full, Almost-Full, Half-Full,

Contextual Info: QS72215, QS72225 Q High-Speed. . .CMOS 512x 1 8, 1 K x 1 8 Parallel Clocked FIFO ne7, . 1c QS72215 QS72225 FEATURES • CMOS dual-port SRAM technology, 512 x 18 or 1024x 18 • Fast cycle times: 20/25/35 ns • Choice of standard or enhanced operating mode

Contextual Info: QS72215, QS72225 Ô High-Speed CMOS 512 x 1 8 ,1K x 18 Parallel Clocked FIFO QS72215 QS72225 FEATURES • CMOS dual-port SRAM technology, 512 x 18 or 10 24x 18 • Fast cycle times: 20/25/35 ns • Choice of standard or enhanced operating mode • Device comes up into one of two known default

CY7C408A

Abstract: CY7C409A inverter 2001v CY7C409A-25PC
Contextual Info: CY7C408A CY7C409A 64 x 8 Cascadable FIFO 64 x 9 Cascadable FIFO Features D D D D D D D D D D D AFE is HIGH when the FIFO is almost full or almost empty, otherwise AFE is LOW. HF is HIGH when the FIFO is half full, otherwise HF is LOW. 64 x 8 and 64 x 9 firstĆin firstĆout

SH 6770

Contextual Info: 1.0 Product Description 1.1 Overview The B t8 2 l5 is a bidirectional buffer with a 36-bit bidirectional port and 9-bit uni­ directional ports that can be configured to transfer iixed-length cells. Bach direc­ tion can store up to 512 36-bit words. This part, therefore, replaces eight

QS72215

Abstract: DESIGN AND IMPLEMENTATION OF SYNCHRONOUS FIFO QS32383 QS3383
Contextual Info: QS72215, QS72225 High-Speed CMOS High Speed CMOS 512Bus x 18,Exchange 1K x 18 Parallel Clocked SwitchesFIFO Q QS3383 QS72215 QS32383 QS72225 FEATURES • CMOS dual-port SRAM technology, 512 x 18 or 1024 x 18 • Fast cycle times: 20/25/35 ns • Choice of standard or enhanced operating

Contextual Info: LH540215/25 FEATURES 512 x 18 /1 0 2 4 x 18 Synchronous FIFO • May be Cascaded for Increased Depth, or Paralleled for Increased Width • Fast Cycle Times: 20/25/35 ns • Five Status Flags: Full, Almost-Full, Half-Full, Almost-Empty, and Empty; ‘Almost’ Flags are

Contextual Info: QS72215, QS72225 Q High-Speed CMOS 512 X 1 8 ,1K X 18 Parallel Synchronous FIFO QS72215 QS72225 FEATURES • Fast Cycle Times 20/25/35 ns • Pin-Compatible Drop-In Replacements for IDT72215LB/25LB FIFO's • Choice of Standard or Enhanced Operating Mode • Device Comes Up into One of Two Known Default

Contextual Info: LH540215/25 SHARP 512 x 18/1024 x 18 Synchronous FIFO Data Sheet • May be Cascaded for Increased Depth, or Paralleled for Increased Width FEATURES • Fast Cycle Times: 20/25/35 ns • 16-mA-loL Three-State Outputs • Pin-Compatible Drop-In Replacements for

02A4

Abstract: A001 XP2-17 single port RAM
Contextual Info: LatticeXP2 Memory Usage Guide November 2008 Technical Note TN1137 Introduction This technical note discusses memory usage for the LatticeXP2 device family. It is intended to be used by design engineers as a guide for integrating the User TAG, EBR- Embedded Block RAM and PFU-based memories in this

CY7C408A-35DC

Abstract: CY7C408A-25KMB inverter 2001v C403A-2 CY7C408A CY7C409A CY7C409A-25DC CY7C409A-25KMB CY7C409A25DC
Contextual Info: bSE D CYPRESS SEMICONDUCTOR 25ê^bb2 GGlObl? 510 • CYP CY7C408A CY7C409A P Y P P ïïQ C ’ Cascadable 64 x 8 FIFO Cascadable 64 x 9 FIFO SEMICONDUCTOR Features • 64 x 8 and 64 x 9 first-in first-out FIFO buffer memory • 35-MIIz shift in and shift out rates