FIFO CASCADE DEPTH POINTER Search Results

ring COUNTER

Abstract: AN-69 IDT72211 IDT72215 IDT72225
Contextual Info:  Integrated Device Technology, Inc. DEPTH EXPANSION OF IDT'S SYNCHRONOUS FIFOs USING THE RING COUNTER APPROACH APPLICATION NOTE AN-69 By Bhanu V. R. Nanduri INTRODUCTION This application note describes a concise design approach to expand in depth IDT’s synchronous FIFOs. As an example

XAPP698

Abstract: XC2064 XC2VP100 XC2VP20 XC2VP30 XC2VP40 XC3090 XC4005 XC5210
Contextual Info: Mesh Fabric Reference Design Application Note XAPP698 v1.2 February 15, 2005 R R "Xilinx" and the Xilinx logo shown above are registered trademarks of Xilinx, Inc. Any rights not expressly granted herein are reserved. CoolRunner, RocketChips, Rocket IP, Spartan, StateBENCH, StateCAD, Virtex, XACT, XC2064, XC3090, XC4005, and XC5210 are

CY7C371

Abstract: CY7C4421 CY7C4425 depth expansion fifo pointer read write four
Contextual Info: Depth Expansion of Synchronous FIFOs Introduction Applications often require FIFO buffers deeper than those offered by discrete devices. By depth expanding multiple devices, a logically deeper FIFO can be constructed. The synchronous FIFO family offers two approaches to this common

fifo vhdl

Abstract: synchronous fifo CY7C371 CY7C4421 CY7C4425 depth expansion fifo pointer read write four
Contextual Info: fax id: 5507 Depth Expansion of Synchronous FIFOs Introduction Applications often require FIFO buffers deeper than those offered by discrete devices. By depth expanding multiple devices, a logically deeper FIFO can be constructed. The synchronous FIFO family offers two approaches to this common

Contextual Info: AN-26: Q S722X5 FAMILY, DESIGNER-FRIENDLY, 18-BIT-W IDE CLOCKED FIFOS Q The QS722X5 Family: — i- • . Designer-Friendly, 18-Bit-Wide Clocked FIFOs INTRODUCTION The new Quality Sem iconductor QS722X5farnily 18-bit-wide First-In, First-Out memories FIFOs are high-speed, synchronous digital

RJH 32

Contextual Info: 512 x 18/1024 x 18 Synchronous FIFO FEATURES • May be Cascaded for Increased Depth, or Paralleled for Increased Width • Fast Cycle Times: 20/25/35 ns • 16-mA-l<x Three-State Outputs • Pin-Compatible Drop-In Replacements for IDT72215B/25B FIFOs • Choice of IDT-Compatible or Enhanced Operating

Contextual Info: QS7223, QS7224 2Kx9a 4Kx9: High Speed CMOS 9-bit Clocked FIFO Q QS7223 QS7224 1 MPnABDM v^ INFORMATION FEATURES/BENEFITS • Clocked interface FIFOs for high speed systems • Data and flags change on rising edge of clocks • Fully Asynchronous Read and Write

fifo flag read write empty full buffer cascade er

Contextual Info: LH540215/25 SHARP Data Sheet 512x18/1024 x 18 Synchronous FIFO FEATURES • May be Cascaded for Increased Depth, or Paralleled for Increased Width • Fast Cycle Times: 20/25/35 ns • 16-m A -loL Three-State Outputs • Pin-Compatible Drop-In Replacements for

68-PIN

Abstract: LH540215 LH540225 D1591
Contextual Info: LH540215/25 512 x 18 / 1024 × 18 Synchronous FIFO • May be Cascaded for Increased Depth, or FEATURES Paralleled for Increased Width • Fast Cycle Times: 20/25/35 ns • Pin-Compatible Drop-In Replacements for • Five Status Flags: Full, Almost-Full, Half-Full,

Contextual Info: QS72215, QS72225 Q High-Speed CMOS 512 X 1 8 ,1K X 18 Parallel Synchronous FIFO QS72215 QS72225 FEATURES • Fast Cycle Times 20/25/35 ns • Pin-Compatible Drop-In Replacements for IDT72215LB/25LB FIFO's • Choice of Standard or Enhanced Operating Mode • Device Comes Up into One of Two Known Default

25bco

Abstract: LH540215 LH540225 GAL20ra10
Contextual Info: LH540215/25 512 x 18 / 1024 × 18 Synchronous FIFO • May be Cascaded for Increased Depth, or FEATURES Paralleled for Increased Width • Fast Cycle Times: 20/25/35 ns • Pin-Compatible Drop-In Replacements for • 16-mA-IOL Three-State Outputs • Five Status Flags: Full, Almost-Full, Half-Full,

Contextual Info: QS72215, QS72225 Q High-Speed. . .CMOS 512x 1 8, 1 K x 1 8 Parallel Clocked FIFO ne7, . 1c QS72215 QS72225 FEATURES • CMOS dual-port SRAM technology, 512 x 18 or 1024x 18 • Fast cycle times: 20/25/35 ns • Choice of standard or enhanced operating mode

Contextual Info: QS72215, QS72225 Ô High-Speed CMOS 512 x 1 8 ,1K x 18 Parallel Clocked FIFO QS72215 QS72225 FEATURES • CMOS dual-port SRAM technology, 512 x 18 or 10 24x 18 • Fast cycle times: 20/25/35 ns • Choice of standard or enhanced operating mode • Device comes up into one of two known default

diode 7654

Contextual Info: QS7223, Q QS7224 2K x 9" QS7223 4Kx9: QS7224 advance INFORMATION High Speed CMOS 9-bit Clocked FIFO FEATURES/BENEFITS • • • • • Clocked interface FIFOs for high speed systems Data and flags change on rising edge of clocks Fully Asynchronous Read and Write

Contextual Info: LH540215/25 SHARP 512 x 18/1024 x 18 Synchronous FIFO Data Sheet • May be Cascaded for Increased Depth, or Paralleled for Increased Width FEATURES • Fast Cycle Times: 20/25/35 ns • 16-mA-loL Three-State Outputs • Pin-Compatible Drop-In Replacements for

QS72215

Abstract: DESIGN AND IMPLEMENTATION OF SYNCHRONOUS FIFO QS32383 QS3383
Contextual Info: QS72215, QS72225 High-Speed CMOS High Speed CMOS 512Bus x 18,Exchange 1K x 18 Parallel Clocked SwitchesFIFO Q QS3383 QS72215 QS32383 QS72225 FEATURES • CMOS dual-port SRAM technology, 512 x 18 or 1024 x 18 • Fast cycle times: 20/25/35 ns • Choice of standard or enhanced operating

LH540235

Abstract: LH540245 LH543620
Contextual Info: LH540235/45 2048 x 18 / 4096 × 18 Synchronous FIFOs • May be Cascaded for Increased Depth, or FEATURES Paralleled for Increased Width • Fast Cycle Times: 20/25/35 ns • Pin-Compatible Drop-In Replacements for • 16 mA-IOL High-Drive Three-State Outputs

Contextual Info: LH540235/45 FEATURES • Fast Cycle Times: 20/25/35 ns • Pin-Compatible Drop-In Replacements for IDT72235B/45B FIFOs • Choice of IDT-Compatible or Enhanced Operating Mode; Selected by an Input Control Signal • Device Comes Up into One of Two Known Default

PEm 0549

Contextual Info: SH A R P Data Sheet LH540235/45 2048 x 18 / 4096 x 18 Synchronous FIFOs FEATURES • Fast Cycle Times: 20/25/35 ns • Pin-Compatible Drop-In Replacements for IDT72235B/45B FIFOs • May be Cascaded for Increased Depth, or Paralleled for Increased Width •

Contextual Info: CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT FEATURES: • First-In/First-Out dual-port memory • 64 x 4 organization IDT72401/03 • 64 x 5 organization (IDT72402/04) • IDT72401/02 pin and functionally compatible with MM 167401/02 • RAM-based FIFO with low fall-through time

IDT72401

Abstract: IDT72403
Contextual Info: IDT72401 IDT72403 CMOS PARALLEL FIFO 64 x 4 and 64 x 5 FEATURES: • • • • • • • • • • • • • • • • has an Output Enable OE pin. The FlFOs accept 4-bit data at the data input (D0-D3). The stored data stack up on a first-in/first-out basis.

IDT72401

Abstract: IDT72402 IDT72403 IDT72404
Contextual Info: IDT72401 IDT72402 IDT72403 IDT72404 CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT Integrated Device Technology, Inc. FEATURES: • • • • • • • • • • • • • • • • • First-ln/First-Out Dual-Port memory 64 x 4 organization IDT72401/03

Contextual Info: CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT FEATURES: • • • • • • • • • • • • • • • • • IDT72401 IDT72402 IDT72403 IDT72404 O utput Enable QE pin. The FIFOs accept 4-bit or 5-bit data at the data input (Do-D3,4). The stored data stack up on a firstin/first-out basis.

Contextual Info: IDT72401 IDT72403 CMOS PARALLEL FIFO 64 x 4 and 64 x 5 FEATURES: • • • • • • • • • • • • • • • • • First-ln/First-Out memories organized 64 words by 4 bits. The IDT72403 also has an Output Enable OE pin. The FlFOs accept 4-bit data at the data input