FIBER OPTIC REGENERATOR 28 Search Results

Contextual Info: ANALOG DEVICES Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming AD808 FEATURES Meets CCITT G.958 Requirements for STM-4 Regenerator—Type A Meets Bellcore TR-NWT-000253 Requirements for OC-12 Output Jitter: 2.5 Degrees RMS 622 Mbps Clock Recovery and Data Retiming

Contextual Info: ANALO G DEVICES Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming AD807 FEATURES Meets CCITT G.958 Requirements for STM-1 Regenerator—Type A Meets Bellcore TR-NWT-000253 Requirements for OC-3 Output Jitter: 2.0 Degrees RMS 155 Mbps Clock Recovery and Data Retiming

807155

Abstract: a3607 1A227 EPITAXX erm
Contextual Info: AN ALO G D E V IC E S Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming A3607 FEATURES M eets CCITT G.958 Requirements for STM-1 Regenerator—Type A M eets Bellcore TR-NW T-000253 Requirem ents for OC-3 O utput Jitter: 2.0 Degrees RMS

Contextual Info: ANALO G D E V IC E S Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming AD807 FEATURES Meets CCITT G.958 Requirements for STM-1 Regenerator—Type A Meets Bellcore TR-NWT-000253 Requirements for OC-3 Output Jitter: 2.0 Degrees RMS 155 Mbps Clock Recovery and Data Retiming

AN649

Abstract: MAX3664 MAX3667 MAX3675 MAX3680 MAX3681 MAX3691 MAX3766 Fiber Optic regenerator 28
Contextual Info: FIBER OPTIC CIRCUITS Application Note 649: Jun 28, 2000 HFTA-04.0: Optical/Electrical Conversion in SDH/SONET Fiber Optic Systems This article explains the basic functions and design challenges of the optical to electrical and electrical to optical signal conversion in SDH/SONET fiber optic

E1 to fiber optic converter circuit

Abstract: LEVEL ONE COMMUNICATIONS SSI 7200 sxt multiplexer LP-UNEQ microwave movement detection 2E11-1 2E111 Signal path designer
Contextual Info: Application Note 9801 SXT6051/SXT6251 SDH Chipset FEBRUARY 1998 Revision 1.0 SDH Specifications and ITU Standards SDH and ITU Specifications The original goal of the Standards Committee was to establish an international specification for a common hierarchy

4501 ic

Abstract: fec 34 regenerator in optical ADN2809 OC48 PRBS23 PRBS-23
Contextual Info: ADN2809—Multirate Limiting Amplifier and Clock and Data Recovery IC The ADN2809’s proprietary delay and phase-locked loop architecture ensures that every SONET/SDH jitter requirement is exceeded over all operating conditions. Low bandwidth jitter transfer simultaneous

100 pin scsi

Abstract: MS17
Contextual Info: SCSI Converter Models MS16, MS17 Expand the functionality of LVD/MSE and SE SCSI SCSI Product Locator NEW! Series 80 Models MS16, MS17 LVD/MSE to SE Converter Paralan’s Series 80 Models MS16 / MS17 - Expand the functionality of LVD/MSE and SE SCSI in several

Nortel OC-48 TransportNode

Abstract: Nortel OC-48 classic junglemux Lucent truewave Lucent truewave plus Lucent truewave classic Nortel mor plus Nortel OC192 DISPERSION shifted FIBER NZDSF
Contextual Info: S/DMS TransportNode Advanced Optical Networking Solutions for Global High-Capacity Transport Applications For more information, contact your local Nortel Networks account representative, or call 1-800-4 NORTEL 1-800-466-7835 or 506-674-5470. In the United States:

amcc CDR

Abstract: S3052 MPC860 d412 "pin compatible"
Contextual Info: Part Number 3052 Revision NC - Aug. 4, 1999 S3052 PRODUCT BRIEF DATA SHEET Multi-Rate Performance Monitor S3052 Features • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • Single 3.3V supply

Nortel OC-48 TransportNode

Abstract: Nortel OC-48 classic tx nortel oc-192 biolas D dms transportnode opc Nortel EDFA TransportNode DMS URBAN GR-1230 network rerouting
Contextual Info: Your total SONET transport solution with proven advantages in any network environment AT A G L A N C E S/DMS TransportNode Overview Your total SONET transport solution with proven advantages in any network environment W ith today’s service providers faced with the twin

STM-16 LIU

Abstract: GR-1400 GR-1400-CORE
Contextual Info: PHAST-12E Device Programmable, High-Performance ATM/PPP/TDM SONET/SDH Terminator for Level 12 with Enhanced Features TXC-06212 TECHNICAL OVERVIEW PRODUCT PREVIEW • Supports simultaneous termination of ATM, POS, and TDM traffic • Integrated clock recovery and synthesis for four 155.52

PREAMPLIFIER TRANSIMPEDANCE optic fet

Abstract: AD8015 TMAX abb AD8015 Circuits PIN-TIA 1a227 simple circuit diagram of electronic choke 1/3 phase common mode choke C2044 hafo
Contextual Info: a Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming AD807 frequency acquisition without false lock. This eliminates a reliance on external components, like a crystal or a SAW filter, to aid frequency acquisition. FEATURES Meets CCITT G.958 Requirements

1A227

Abstract: AD8015 hafo XFC-B MICA WAFER AD807 AD807-155BR AD807-155BR-REEL AD807-155BR-REEL7 AD807A-155BR
Contextual Info: a Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming AD807 frequency acquisition without false lock. This eliminates a reliance on external components such as a crystal or a SAW filter, to aid frequency acquisition. FEATURES Meets CCITT G.958 Requirements

DMS URBAN

Abstract: DMS URBAN coded alarms DMS1 URBAN DMS remote carrier urban fault detection broadband network SONET/CROSS-CONNECT OC-24 STM-16 STS-192 STS-48
Contextual Info: About this Document H D S L • I XC • B I S D N • C C I T T • D I D • N A N P • L ATA • M F J • O S I • U N I • V S AT • WAT S • A D S L • F T T C • G S M • H D S L • R H C • S O N E T • T C P / I P • This document is intended for anyone with an interest in advanced networks.

GR-1400

Abstract: GR-496-CORE GR-1400-CORE g803 GR-1400-CORE 1994
Contextual Info: PHAST-12E Device Programmable, High-Performance ATM/PPP/TDM SONET/SDH Terminator for Level 12 with Enhanced Features TXC-06212 DESCRIPTION • Supports simultaneous termination of ATM, POS, and TDM Time Division Multiplexed, e.g., VT1.5, VC-4 etc. traffic

8 pin LM393 ic

Abstract: LM393 data sheet INTERNAL CIRCUIT DIAGRAM OF LM393 LM393 PIN DIAGRAM regenerator in optical ICS1887 LM393
Contextual Info: ICS1887 Integrated Circuit Systems, Inc. FDDI/Fast Ethernet PHYceiver  General Description Features The ICS1887 is designed to provide high performance clock recovery and generation for 125 MHz serial data streams. The ICS1887 is ideally suited for LAN transceiver applications in

ICS1887

Abstract: ICS1887M LM393
Contextual Info: ICS1887 Integrated Circuit Systems, Inc. FDDI / Fast Ethernet PHYceiverTM General Description Features The ICS1887 is designed to provide high performance clock recovery and generation for 125 MHz serial data streams. The ICS1887 is ideally suited for LAN transceiver applications in

Contextual Info: BACK ICS1887 Integrated Circuit Systems, Inc. FDDI / Fast Ethernet PHYceiverTM General Description Features The ICS1887 is designed to provide high performance clock recovery and generation for 125 MHz serial data streams. The ICS1887 is ideally suited for LAN transceiver applications in

lm393 equivalent VALUE IC CIRCUIT

Abstract: Digital Alarm Clock by using ttl INTERNAL CIRCUIT DIAGRAM OF LM393 LM393 data sheet LM393 LM393 PIN DIAGRAM regenerator in optical ICS1887 ICS1887M Fiber Optic regenerator 28
Contextual Info: ICS1887 Integrated Circuit Systems, Inc. FDDI/Fast Ethernet PHYceiver  General Description Features The ICS1887 is designed to provide high performance clock recovery and generation for 125 MHz serial data streams. The ICS1887 is ideally suited for LAN transceiver applications in

TXC-07905

Abstract: AU-AIS MSP SNCP BP-51H TXC-07905BRBG 421L BY274
Contextual Info: OED622 Device Dual STM-4/STM-1 Overhead Terminator, Tributary Processor and Cross-Connect with Integrated E1 Mapper TXC-07905 DATA SHEET DESCRIPTION: ™ The Optimized Edge Device, OED622, is a dual STM-4/STM-1 SDH framer and overhead terminator, virtual

Contextual Info: ICS1887 Integrated Circuit Systems, Inc. K l FDDI/Fast Ethernet PHYceiver TM General Description Features The ICS1887 is designed to provide high performance clock recovery and generation for 125 MHz serial data streams. The ICS1887 is ideally suited for LAN transceiver applications in

Contextual Info: ICS1887 Integrated Circuit Systems, Inc. FDDI / Fast Ethernet PHYceiver General Description Features The ICS1887 is designed to provide high performance clock recovery and generation for 125 MHz serial data streams. The ICS 1887 is ideally suited for LAN transceiver applications in

2ya18

Abstract: nortel demux ya18 FZT968 nortel YA YA19 YA20 AB89 AC10 OC48
Contextual Info: YA18 2.5 Gb/s Clock and Data Recovery Circuit Data Sheet Features Fully balanced, differential architecture from input to output Differential CML data input accepts signals of up to 2.7 Gb/s data rates - 50 Ω terminated 50 Ω terminated differential CML