FBGA 12 X 12 THERMAL RESISTANCE Search Results

MT41K256M32

Abstract: MT41K 256M32 MT41K256M16 MT41K256M32SGB-125M MT41K256M3 MT41K256M MT41K256 MT41K256M16 SPD FBGA DDR3 x32
Contextual Info: Preliminary‡ 8Gb: x32 TwinDie DDR3Lm SDRAM Description TwinDie 1.35V DDR3Lm SDRAM MT41K256M32 – 32 Meg x 32 x 8 Banks Description Options Marking • Configuration – 32 Meg x 32 x 8 banks • FBGA package Pb-free – 136-ball FBGA (10mm x 14mm x 1.2mm) Rev. E

Contextual Info: IS61QDP2B42M18A/A1/A2 IS61QDP2B41M36A/A1/A2 2Mx18, 1Mx36 36Mb QUAD-P Burst 4 SYNCHRONOUS SRAM (2.0 Cycle Read Latency) FEATURES •                    1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid

CY7C1071DV33

Contextual Info: CY7C1071DV33 32-Mbit 2 M x 16 Static RAM 32-Mbit (2 M × 16) Static RAM Features Functional Description • High speed ❐ tAA = 12 ns ■ Low active power ❐ ICC = 250 mA at 83.3 MHz ■ Low Complementary Metal Oxide Semiconductor (CMOS) standby power

Contextual Info: IS61QDP2B42M18A IS61QDP2B41M36A 2Mx18, 1Mx36 36Mb QUAD-P Burst 4 SYNCHRONOUS SRAM (2.0 Cycle Read Latency) FEATURES •                    1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid

Contextual Info: IS61QDPB42M18A IS61QDPB41M36A 2Mx18, 1Mx36 36Mb QUAD-P Burst 4 SYNCHRONOUS SRAM (2.5 Cycle Read Latency) FEATURES •                    1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid

Contextual Info: IS61QDPB41M18A IS61QDPB451236A 1Mx18, 512Kx36 18Mb QUAD-P Burst 4 SYNCHRONOUS SRAM (2.5 Cycle Read Latency) FEATURES •                    512Kx36 and 1Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid

Contextual Info: CY7C1460AV25 CY7C1462AV25 36-Mbit 1 M x 36/2 M × 18 Pipelined SRAM with NoBL Architecture 36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™

Contextual Info: CY14B108L CY14B108N 8-Mbit 1024 K x 8/512 K × 16 nvSRAM 8-Mbit (1024 K × 8/512 K × 16) nvSRAM Features • Packages ❐ 44-/54-pin thin small outline package (TSOP) Type II ❐ 48-ball fine-pitch ball grid array (FBGA) Pb-free and restriction of hazardous substances (RoHS)

Contextual Info: CY7C1441AV33 36-Mbit 1 M x 36 Flow-Through SRAM 36-Mbit (1 M × 36) Flow-Through SRAM Features Functional Description • Supports 133-MHz bus operations ■ 1 M × 36 common I/O ■ 3.3 V core power supply ■ 2.5 V or 3.3 V I/O power supply ■ Fast clock-to-output times

Contextual Info: NOT RECOMMENDED FOR NEW DESIGNS 18Mb: 1 MEG x 18, 512K x 32/36 FLOW-THROUGH ZBT SRAM 18Mb ZBT SRAM MT55L1MY18F, MT55V1MV18F, MT55L512Y32F, MT55V512V32F, MT55L512Y36F, MT55V512V36F 3.3V VDD, 3.3V or 2.5V I/O; 2.5V VDD 2.5V I/O FEATURES • • • • •

MS-026

Abstract: MT55L128L18P1 MT55L128L18P1T-10 MT55L64L32P1 MT55L64L36P1 MT55L128
Contextual Info: 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, PIPELINED ZBT SRAM 2Mb ZBT SRAM MT55L128L18P1, MT55L64L32P1, MT55L64L36P1 3.3V VDD, 3.3V I/O FEATURES • • • • • • • • • • • • • • • • • • • High frequency and 100 percent bus utilization

27934

Contextual Info: CY14B101LA CY14B101NA 1-Mbit 128 K x 8/64 K × 16 nvSRAM 1-Mbit (128 K × 8/64 K × 16) nvSRAM Features • Packages ❐ 32-pin small-outline integrated circuit (SOIC) ❐ 44-/54-pin thin small outline package (TSOP) Type II ❐ 48-pin shrink small-outline package (SSOP)

Contextual Info: NOT RECOMMENDED FOR NEW DESIGNS 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED ZBT SRAM 18Mb ZBT SRAM MT55L1MY18P, MT55V1MV18P, MT55L512Y32P, MT55V512V32P, MT55L512Y36P, MT55V512V36P 3.3V VDD, 3.3V or 2.5V I/O; 2.5V VDD 2.5V I/O FEATURES • • • • • •

Contextual Info: ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED ZBT SRAM 16Mb ZBT SRAM MT55L1MY18P, MT55V1MV18P, MT55L512Y32P, MT55V512V32P, MT55L512Y36P, MT55V512V36P 3.3V VDD, 3.3V or 2.5V I/O; 2.5V VDD 2.5V I/O FEATURES 100-Pin TQFP1 • High frequency and 100 percent bus utilization

Contextual Info: IS61QDB22M18A IS61QDB21M36A 2Mx18, 1Mx36 36Mb QUAD Burst 2 Synchronous SRAM FEATURES •                  1Mx36 and 2Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window.

IS61QDB41M36A

Contextual Info: IS61QDB42M18A IS61QDB41M36A 2Mx18, 1Mx36 36Mb QUAD Burst 4 SYNCHRONOUS SRAM FEATURES •                   1Mx36 and 2Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window.

Contextual Info: IS61QDB41M18A IS61QDB451236A 1Mx18, 512Kx36 18Mb QUAD Burst 4 SYNCHRONOUS SRAM FEATURES •                   512Kx36 and 1Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid

Contextual Info: IS61QDB42M18A IS61QDB41M36A 2Mx18, 1Mx36 36Mb QUAD Burst 4 SYNCHRONOUS SRAM FEATURES •                   1Mx36 and 2Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window.

Contextual Info: IS61QDB41M18A IS61QDB451236A 1Mx18, 512Kx36 18Mb QUAD Burst 4 SYNCHRONOUS SRAM FEATURES •                   512Kx36 and 1Mx18 configuration available. On-chip Delay-Locked loop (DLL) for wide data valid

Contextual Info: IS61QDB24M18A IS61QDB22M36A 4Mx18, 2Mx36 72Mb QUAD Burst 2 Synchronous SRAM FEATURES •                  2Mx36 and 4Mx18 configuration available. On-chip Delay-Locked loop (DLL) for wide data valid window.

Contextual Info: 4Mb: 256K x 18, 128K x 32/36 PIPELINED ZBT SRAM 4Mb ZBT SRAM MT55L256L18P1, MT55L256V18P1, MT55L128L32P1, MT55L128V32P1, MT55L128L36P1, MT55L128V36P1 3.3V VDD, 3.3V or 2.5V I/O FEATURES • • • • • • • • • • • • • • • • •

IS49NLC96400

Contextual Info: IS49NLC96400,IS49NLC18320,IS49NLC36160 576Mb x9, x18, x36 Common I/O RLDRAM 2 Memory ADVANCED INFORMATION FEBRUARY 2012 FEATURES • • • • • • • • • 533MHz DDR operation (1.067 Gb/s/pin data rate) 38.4Gb/s peak bandwidth (x36 at 533 MHz

IS61DDB42M36A

Contextual Info: IS61DDB44M18A IS61DDB42M36A 4Mx18, 2Mx36 72Mb DDR-II Burst 4 CIO SYNCHRONOUS SRAM FEATURES •                  2Mx36 and 4Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid

Contextual Info: CY7C1518KV18 CY7C1520KV18 72-Mbit DDR II SRAM Two-Word Burst Architecture 72-Mbit DDR II SRAM Two-Word Burst Architecture Features Configurations • 72-Mbit density 4 M x 18, 2 M × 36 CY7C1518KV18 – 4 M × 18 ■ 333 MHz clock for high bandwidth CY7C1520KV18 – 2 M × 36