F 7732 Search Results

Contextual Info: Timing Definition For Programmable Delay Lines PDU’s Typical Set-Up Specifications Minimum Input Pulse-Width (ns) “Suggested Recommended Minimum Input Period (ns) 10% o f T dt 25% o f T dt G reater than T dt 2 X PW |N 8% o f T dt 8% o f T dt 2 0% of T dt

Contextual Info: GMM7732O0ÛCT/TG -6/7 LG Semicon Co.,Ltd. 2,097,152 W ORDS x 72 BIT CMOS DYNAMIC RAM MODULE Description Features The G M M 7732000C T /T G is an 2M x 72 bits D ynam ic RA M M O DULE which is assem bled 8 pieces o f 1M x 16bit DRA M s in 44 pin T SO P package, 4 pieces o f 1M x

BF sot-89

Abstract: KEC sot89 marking D
Contextual Info: SEM ICONDUCTOR KIA78DS05BP/BF TECHNI CAL DATA BI POL AR LI NEAR I NT E GR AT E D C I R C U I T LO W D R O PO U T VOLTAGE REG ULATO R. The K.IA78DS05 series consists o f positive fixed output voltage regulator IC capable o f sourcing current up to 30mA. Due to the features o f low dropout voltage and low standby

Contextual Info: Programmable Delay Units PDU"713 SERIES: T 2L I n t e r f a c e d 3 BIT data delay \p / devieesYinc. Sli ! ! F e a tu re s : • D ig ita lly p r o g r a m m a b le in 8 d e la y s te p s . ■ F its s ta n d a rd 1 4 p in s D IP s o c k e t. m In p u t & o u tp u ts f u lly T T L in te r fa c e d & b u ffe re d .

WASHING machine controller

Abstract: 7721 adc
Contextual Info: • 1 6 -B IT MICROCOMPUTERS # Each Product fields o f application f 1' Type Features life Built-in wide use ROM type 16K-60K ROM Inverter drive type Three-phase output, phase detection function Strengthen type for analog function 10bit Built in ADC Built-in DMA

Contextual Info: - F a s t Lo g ic Digital Delay Units tEurc D D IM F Features: • Auto-insertable. ■ Com pletely interfaced with TTL and DTL application. ■ No external com ponents required. ■ P.C. board space econom y achieved. ■ Fits standard 14 pins DIP socket.

Contextual Info: Digitally Programmable Delay Lines series : PDU-2600 DIP PDU-2600S |(SMD) 'a m v j U'9h Accuracy1 ,See App|icati0n No|esCompensated 1&2 f,e(luency Test Conditions (for F, • Input pulse-width: > 150% of max. delay. ■ Input pulse spacing: > 3 times of max. delay.

Contextual Info: data \f% \ delay N o/ devicesYinc. Digital Delay Units SERIES: DDU-4 1 to 5 Taps 14 pins DIP T 2L Interfaced F e a tu re s : • Com pletely interfaced for TTL and DTL application. ■ No external com ponents required. ■ P. C. board space econom y achieved.

Contextual Info: HARRIS HPL-77319/16LE8 H PL-77320/16HE8 w Preliminary H p L H a rris P r o g ra m m a b le L o g ic Features • L O G IC P A T H S T E S T E D T O E N S U R E F U N C T IO N A L IT Y • F A S T A C C ES S IN P U T T O O U T P U T 3 5 nsec M A X

32F2

Contextual Info: ia s f L o g ic 2-Phase Gated-Delay Line Oscillator S ER IES : 14 pins DIP T T L Interfaced DL0-32F data delay devices?inc. F e a tu re s : • ■ ■ ■ ■ ■ ■ ■ Auto-insertable. TTL interfaced. Continuous or keyable wavetrain. Locked syncronization achieved with

Contextual Info: ïF a s f L o g ic data Noya Programmable Delay Units delay W devicesVinc 8 Bit T T L Interfaced SERIES: P D U 1 - 8 F Specifications: -rïl Features: • Input & Output TTL buffered ■ 8-B it TTL program m able delay line ■ Two (2) Separate outputs; inverting

4 MHz Oscillator

Abstract: 40 MHZ OSCILLATOR 30F-30
Contextual Info: F a s t L o g ic Gated-Delay Line Oscijlator O -3 1 F SERIES. nU iLU Ol r 1 4 p in sD IP TTL Interfaced o c d ic c Features: • ■ ■ ■ Auto-insertable. T 2L interfaced. Continuous or keyable wavetrain. Locked syncronization achieved with random gating signal.

Contextual Info: IF a s f Logic Digital Delay Units SERIES: DDU-4F I ' 1 » J 1»* t ’ 4 "ìnS “'I T T L Interfaced F e a tu re s : • Auto-insertable. ■ Com pletely interfaced with TTL and DTL application. ■ No external com ponents required. ■ P.C. board space econom y achieved.

13F4C

Abstract: st schottky
Contextual Info: ra s f L o g ic Programmable Delay Lines SERIES: PDU-13F 3 BIT T 2L Interfaced F e a tu re s : • ■ ■ ■ ■ ■ ■ Digitally program m able in 8 delay steps. Fits standard 14 pins DIF* socket. Input & outputs fully TTL interfaced & buffered. Two (2) separate outputs; inverting & non-inverting.

ZENER A33

Abstract: pulse 0030 a36 zener CA 3390 b72 zener V0 3150 S381206 ZENER A34
Contextual Info: Data Sheets of AVA Technology Chip Type White LED Model : S381206 AVA Technology CO., LTD. 2640 S. Myrtle Ave. Suite 6 Monrovia, CA 91016, USA P: 626-574-7726 F: 626-574-7732 http://www.led4life.com AVA Technology S381206 Power Side Lighting LED with Reflector

T3228D1

Contextual Info: Data Sheets of AVA technology SMD Type White LED Model : T3228D1 AVA technology CO. 2640 S. Myrtle Ave., Suite 6 Monrovia, CA 91016 P: 626-574-7726 F: 626-574-7732 http://www.led4life.com AVA Technology T3228D1 Top View LED with Reflector 1. FEATURES • ·

T3228D3

Contextual Info: Data Sheets of AVA Technology SMD Type White LED Model : T3228D3 AVA Technology Co. 2640 S. Myrtle Ave., Suite 6 Monrovia, CA 91016, USA P: 626-574-7726 F: 626-574-7732 http://www.led4life.com AVA technology T3228D3 Top View LED with Reflector 1. FEATURES

ZENER A33

Abstract: a36 zener b72 zener ZENER A34 S401408 u26f
Contextual Info: Data Sheets of AVA Technology Chip Type White LED Model : S401408 AVA Technology Co. 2640 S. Myrtle Ave. Suite 6 Monrovia, CA 91016, USA P: 626-574-7726 F: 626-574-7732 http://www.led4life.com AVA Technology S401408 Power Side Lighting LED with Reflector

transistor k52

Abstract: k44 transistor T222F transistor k08 transistor k49 S281208
Contextual Info: Data Sheets of AVA Technology Chip Type White LED Model : S281208 AVA Technology CO., LTD. 2640 S. Myrtle Ave. Suite 6 Monrovia, CA 91016, USA P: 626-574-7726 F: 626-574-7732 http://www.led4life.com AVA Technology S281208 Power Side Lighting LED with Reflector

Contextual Info: data delay devicesYinc. E F a s f L o g i c Programmable Pulse IS o n p ra tn r s e r ie s : U C IIC ia iU I 6 Bit T T L Interfaced Features: • Precise pulse width. ■ Inverted & non-inverted outputs. ■ 6-BIT address. ■ 1 ns to 10 ns incremental steps.

transistor c3150

Abstract: c3271 KEMA KEUR thermostat C4108
Contextual Info: What’s New? E X PA N D E D C O M P E T I T I V E O F F E R I N G S Cross-Reference & Online Spec Sheets We have expanded our Carol Brand Electronics offering and now have more competitive crosses than anyone. Many of these cables are in stock and ready for

Contextual Info: Digital Delay Units SERIES DDU-11H 5 Taps ECL Interfaced Test Conditions: • ■ ■ ■ Input pulse-w idth: 150% o f to ta l delay. Input pulse rise-tim e: « 6 ns. Input pulse voltage: .7V R ise-tim e m easured from 20% to 80% of leading edge. ■ Delay tim e measured at 50% o f leading edge.

5050 smd

Abstract: 40XA ACED
Contextual Info: H C M O S — Logic Surface Mounted Delay Line ¡S f "* 0 F e a tu re s : • Designed for surface mounting. ■ Low profile .1 7 5 max. height. ■ Com pletely interfaced HCMOS. Specifications: ■ No. Taps: 5 equally sp aced taps. ■ Total delay tolerance: ± 5 % or 2 ns w hichever s greater.

Contextual Info: F a s t L o g ic Multiple Digital Delay Units MDU-28 F S ER IES : 8 pins DIP T T L Interfaced data delay W devices;Inc. Features: • ■ ■ ■ ■ ■ A uto-insertable. Low cost. C o m p le te ly in terfaced for TTL. Low profile. Fits standard 8 pins DIP socket.