EXO 3 4 F Search Results

EXO-3C

Abstract: 22.1184 48000 25FD EXO3C exo3
Contextual Info: Programmable Oscillator EXO-3C Specifications Product Parameters Package style: 8 7 6 5 7.00 max 1.60Ø 1 2 3 4 12.80 (max) 7.62 0.51 (min) 5.08 (max) 2.50 (min) 1.52 2.54 0~15° 0.60 (max) PIN CONNECTIONS 1 Original freq. 5 Select 1, see table 2 Divided freq.

ex03

Abstract: ex03 kss 0/EXO3 16.000M exo3
Contextual Info: Crystal Oscillator Kss EXO-3 C M O STklU gJiS/C M O S Crystal Oscillator W ^ H /F e a tu re s *?t<D?\ • • # f f 1 /2 ~ 1 /2 8( 1 /2 5 6 ) ^ ) il ^ s e > n s T o l m j u \ 50±2% wf*3TT o . 1 .5 m s e c .« T r o ^ ( ,'£ f t it # 1 4 7 T o • •

ECH35

Abstract: Mullard rfft FCH35
Contextual Info: ECH35 TRIODE H EXO D E Triode hexode fo r use as frequency changer in A .C . mains-operated receivers. The hexode section is designed fo r A.V .C . HEATER Vh Ih 6 .3 0 .3 V A CAPACITANCE3 Hex ode Triod« cgt- g l °gl-lc ca_k ca. gi og.jt Oj-ic « a-g l «

2501 BRIDGE SMD

Abstract: High Voltage Driver IC for HID Lamps Electronic ignitors for HID lamp circuits Thermal Shut Down Functioned MOSFET wien bridge SO24 UBA2030T Wien Bridge Oscillator with RC bridge hid lamp ignitor application notes
Contextual Info: INTEGRATED CIRCUITS DATA SHEET UBA2030T Full bridge driver IC Preliminary specification Supersedes data of 1997 Sep 16 File under Integrated Circuits, IC11 1999 Aug 10 Philips Semiconductors Preliminary specification Full bridge driver IC UBA2030T FEATURES

Contextual Info: S1F71200 Series DESCRIPTION FEATURES S1F71200 is a step-up/step-down DC/DC converter control IC for which the CMOS process is used and to which a power transistor is connected outside. S1F71200 is composed of an oscillator, a reference voltage circuit, an error amplifier, a PWM circuit, a series regulator, a driver, etc. When this IC drives an external power transistor, S1F71200 can constitute a stepup/step-down DC/DC converter that operates as a [stepdown] series regulator when the input voltage is High

xILINX ISE ALLIANCE SOFTWARE 4.2i

Abstract: SPARTAN 6 readback Xilinx jtag cable Schematic HW130 HW-130 X12604 fpga JTAG Programmer Schematics XAPP017 XAPP098 XAPP122
Contextual Info: Application Note: Spartan and SpartanXL Families R XAPP126 v1.2 July 22, 2003 Summary Data Generation and Configuration for Spartan Series FPGAs Author: Ashok Chotai and Hari Devanath This application note describes various methods for configuring Spartan series FPGAs. Each

XC4000X

Contextual Info: R ALLIANCE Series Software A2.1i FPGA Design Implementation Flow sedif, sxnf, edif, edn, edf, xnf, nmc, ncf Options Main Flow NGDBuild ucf Static Timing Analysis ngd map.ncd/ ncd, pcf FPGA Editor ncd, pcf, nmc FPGA Editor NMC Physical Macro ncd, pcf NGDBuild

Xilinx jtag cable Schematic

Abstract: Xilinx usb cable Schematic jtag programmer guide usb programmer xilinx free XAPP501 HW-130 XAPP058 XC17S00 XC18V00 XC9500
Contextual Info: and Application Note: Xilinx Families R Configuration Quick Start Guidelines Author: Stephanie Tapp XAPP501 v1.3 June 10, 2002 Summary This application note discusses the configuration and programming options for Xilinx Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA), and PROM

ex-nor

Abstract: MCI d 302 exnor MC10100 C101 MC10102 MC10103 MC10105 MC10106 MC1011
Contextual Info: MECL 10.000 semes INTEGRATED CIRCUITS FROM MOTOROLA M C 10 ,1 0 0 /1 0 ,2 0 0 Series -3 0 to + 8 5 °C WIC10 ,5 0 0 /1 0 ,6 0 0 Series (-5 5 to + 1 2 5°C ) C irc u it design w ith M E C L 1 0 ,0 0 0 is unusually con­ venient. The d iffe re n tia l a m p lifie r in p u t and e m itterfo llo w e r o u tp u t p e rm it high fa n o u t, th e w ired-O R o p tio n ,

IDT72T51233

Abstract: IDT72T51243 IDT72T51253
Contextual Info: 2.5V MULTI-QUEUE FIFO 4 QUEUES 18 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits FEATURES: • • • • • • • • • • • • • • • Choose from among the following memory density options: IDT72T51233  Total Available Memory = 589,824 bits

IDT72T51433

Abstract: IDT72T51443 IDT72T51453
Contextual Info: 2.5V MULTI-QUEUE FIFO 16 QUEUES 18 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits FEATURES: • • • • • • • • • • • • • • • • Choose from among the following memory density options: IDT72T51433  Total Available Memory = 589,824 bits

IDT72T51333

Abstract: IDT72T51343 IDT72T51353
Contextual Info: 2.5V MULTI-QUEUE FIFO 8 QUEUES 18 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits FEATURES: • • • • • • • • • • • • • • • Choose from among the following memory density options: IDT72T51333  Total Available Memory = 589,824 bits

72T51543

Abstract: 72T51553 IDT72T51543 IDT72T51553
Contextual Info: 2.5V MULTI-QUEUE FIFO 32 QUEUES 18 BIT WIDE CONFIGURATION 1,179,648 bits 2,359,296 bits FEATURES: • • • • • • • • • • • • • • • • Choose from among the following memory density options: IDT72T51543  Total Available Memory = 1,179,648 bits

IDT72T51236

Abstract: IDT72T51246 IDT72T51256
Contextual Info: 2.5V MULTI-QUEUE FIFO 4 QUEUES 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits FEATURES: • • • • • • • • • • • • • • • Choose from among the following memory density options: IDT72T51236  Total Available Memory = 589,824 bits

IDT72T51336

Abstract: IDT72T51346 IDT72T51356
Contextual Info: 2.5V MULTI-QUEUE FIFO 8 QUEUES 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits FEATURES: • • • • • • • • • • • • • • • Choose from among the following memory density options: IDT72T51336  Total Available Memory = 589,824 bits

72T51436

Abstract: 72T51446 IDT72T51436 IDT72T51446 IDT72T51456 multi-queue
Contextual Info: 2.5V MULTI-QUEUE FIFO 16 QUEUES 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits FEATURES: • • • • • • • • • • • • • • • • Choose from among the following memory density options: IDT72T51436  Total Available Memory = 589,824 bits

CTI Communication Techniques

Abstract: TCM8000 d408
Contextual Info: TCM8000 CELLULAR TELEPHONE AUDIO PROCESSOR SCTS041A – D4086, AUGUST 1992 – REVISED APRIL 1993 • • • • • • DCLK DATA RXO REF V BRX V CC VBTX LOAD PSO TXSUM TXO Integrated RX and TX Voice Filters Integrated RX and TX Data Filters Narrow-Band RX SAT Filter

preamplifier st

Abstract: TCM8000 d408 transistor audio preamplifier circuit diagram
Contextual Info: TCM8000 CELLULAR TELEPHONE AUDIO PROCESSOR SCTS041A – D4086, AUGUST 1992 – REVISED APRIL 1993 • • • • • • DCLK DATA RXO REF V BRX V CC VBTX LOAD PSO TXSUM TXO Integrated RX and TX Voice Filters Integrated RX and TX Data Filters Narrow-Band RX SAT Filter

TCM8000

Contextual Info: TCM8000 CELLULAR TELEPHONE AUDIO PROCESSOR SCTS041A – D4086, AUGUST 1992 – REVISED APRIL 1993 • • • • • • DCLK DATA RXO REF V BRX V CC VBTX LOAD PSO TXSUM TXO Integrated RX and TX Voice Filters Integrated RX and TX Data Filters Narrow-Band RX SAT Filter

Xilinx jtag cable Schematic

Abstract: xilinx jtag cable XSVF Xilinx usb cable Schematic XC2C32A XC3S700A XC95288XL prom xilinx xc9536 firmware XAPP058 6 WAY HEADER JTAG PORT
Contextual Info: Application Note: Xilinx Families R XAPP058 v4.1 March 6, 2009 Summary Xilinx In-System Programming Using an Embedded Microcontroller Contact: Randal Kuramoto Xilinx high-performance CPLD, FPGA, and configuration PROM families provide in-system programmability, reliable pin locking, and IEEE Std 1149.1 (JTAG) boundary-scan test

SH100E

Abstract: siemens SH100E elxr siemens Nand gate SH100E5 TRANSISTOR K 2191
Contextual Info: 7 1991 SIEMENS ASIC Product Description SH100E ECL/CML Gale Amy Family FEATURES • Gate complexities from 1,500 to 16,000 gates ■ 120 ps gate delay, 90 ps differential • 1.5 GHz D flip-flop, 1.7 GHz differential ■ Both ECL and CML macro families ■ TTL I/O available

GSIG

Abstract: T7229 E12E13 257al 229GB
Contextual Info: 257AL Transmit Form atter Features • 2-, 4-, 16-state signaling or inhibit signaling Variable F-bit and parity-bit delays ■ Selectable DS1 1.544 Mb/s or CEPT (2.048 Mb/s) formats TTL-compatible Description The 257AL Transmit Formatter integrated circuit converts 14 bits of parallel data (8 traffic bits, 5

ATT ORCA fpga architecture

Abstract: DB9 jtag cable ATT ORCA fpga 9-pin female connector on board 7Pin din Connector on which pin to connect vcc in db9 connector standard 6-pin JTAG header ATT ORCAs female PCB connector 2x5 7Pin Connector
Contextual Info: ORCA Device Programming Download Cable July 2002 Technical Note TN1009 Introduction The ORCA device family offers many programming options for device configuration. Users can easily incorporate the ORCA Download Cable into their system designs, integrating several modes into one easy-to-use interface for

Contextual Info: 3.3V MULTI-QUEUE FLOW-CONTROL DEVICES 4 QUEUES 18 BIT WIDE CONFIGURATION 589,824 bits 1,179,648 bits 2,359,296 bits • • • • FEATURES: • • • • • • • • • Choose from among the following memory density options: IDT72V51233  Total Available Memory = 589,824 bits