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    EXAMPLE ALGORITHM VERILOG Search Results

    EXAMPLE ALGORITHM VERILOG Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    BQ2031SN-A5TRG4
    		Texas Instruments Switch-mode Lead-Acid Battery Charger with User-Selectable Charge Algorithms 16-SOIC 0 to 0 Visit Texas Instruments Buy
    BQ2031SN-A5TR
    		Texas Instruments Switch-mode Lead-Acid Battery Charger with User-Selectable Charge Algorithms 16-SOIC 0 to 0 Visit Texas Instruments Buy
    BQ2031SN-A5
    		Texas Instruments Switch-mode Lead-Acid Battery Charger with User-Selectable Charge Algorithms 16-SOIC 0 to 0 Visit Texas Instruments Buy
    BQ2031PN-A5
    		Texas Instruments Switch-mode Lead-Acid Battery Charger with User-Selectable Charge Algorithms 16-PDIP 0 to 0 Visit Texas Instruments Buy
    BQ2031PN-A5E4
    		Texas Instruments Switch-mode Lead-Acid Battery Charger with User-Selectable Charge Algorithms 16-PDIP 0 to 0 Visit Texas Instruments Buy

    EXAMPLE ALGORITHM VERILOG Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    verilog code for implementation of des

    Abstract: Data Encryption Standard DES
    Contextual Info: FIPS 46-3 Standard Compliant Encryption/Decryption performed in 48 cycles ECB mode DES3 Up to 168 bits of security Triple Data Encryption Standard Megafunction Verilog IP Megafunction The DES3 megafunction implements the Triple Data Encryption Standard (DES3) documented in the U.S. Government publication FIPS 46-3.


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    667 ecb

    Abstract: verilog code for implementation of des verilog code for des tsmc sram
    Contextual Info: FIPS 46-3 Standard Compliant Encryption/Decryption performed in 48 cycles ECB mode DES3 Up to 168 bits of security Triple Data Encryption Standard Core Verilog IP Core The DES3 core implements the Triple Data Encryption Standard (DES3) documented in the U.S. Government publication FIPS 46-3.


    Original     		PDF

    verilog code for des

    Abstract: verilog code for implementation of des inverse quick transformation 0123456789ABCDEF A28E91724C4BBA31
    Contextual Info: FIPS 46-3 Standard Compliant Encryption/Decryption performed in 48 cycles ECB mode DES3 Up to 168 bits of security Triple Data Encryption Standard Core Verilog IP Core The DES3 core implements the Triple Data Encryption Standard (DES3) documented in the U.S. Government publication FIPS 46-3.


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    XIP2031

    Abstract: data encryption standard vhdl
    Contextual Info: Triple DES Encryption Core April 15, 2003 Product Specification AllianceCORE Facts Core Specifics See Table 1 Provided with Core Documentation Product data sheet Design File Formats EDIF Netlist, or VHDL or Verilog Source RTL available at extra cost Constraints File


    Original     		1076-Compliant XIP2031 data encryption standard vhdl PDF

    verilog code for implementation of des

    Abstract: 3S1200E-4 verilog code for des
    Contextual Info: FIPS 46-3 Standard Compliant DES Data Encryption Standard Core Encryption/Decryption performed in 16 cycles ECB mode 56 bits of security For use in FPGA or ASIC designs Verilog IP Core Non Pipelined version Small gate count The DES core implements the Data Encryption Standard (DES) documented in the U.S.


    Original     		0x0123456789abcdef 0x4e6f772069732074 0x68652074696d6520 0x666f7220616c6c20 0x3fa40e8a984d4815 0x6a271787ab8883f9 0x893d51ec4b563b53 verilog code for implementation of des 3S1200E-4 verilog code for des PDF

    verilog code for implementation of des

    Abstract: verilog code for des tsmc sram des verilog RTL 604
    Contextual Info: FIPS 46-3 Standard Compliant DES Data Encryption Standard Core Encryption/Decryption performed in 16 cycles ECB mode 56 bits of security For use in FPGA or ASIC designs Verilog IP Core Non Pipelined version Small gate count The DES core implements the Data Encryption Standard (DES) documented in the U.S.


    Original     		0x0123456789abcdef 0x4e6f772069732074 0x68652074696d6520 0x666f7220616c6c20 0x3fa40e8a984d4815 0x6a271787ab8883f9 0x893d51ec4b563b53 verilog code for implementation of des verilog code for des tsmc sram des verilog RTL 604 PDF

    la 4451

    Abstract: verilog code for implementation of des cycloneIII ep2c20 EP2C20-6
    Contextual Info: FIPS 46-3 Standard Compliant DES Data Encryption Standard Megafunction Encryption/Decryption performed in 16 cycles ECB mode 56 bits of security For use in FPGA or ASIC designs Verilog IP Megafunction Non Pipelined version Small gate count The DES megafunction implements the Data Encryption Standard (DES) documented in


    Original     		0x0123456789abcdef 0x4e6f772069732074 0x68652074696d6520 0x666f7220616c6c20 0x3fa40e8a984d4815 0x6a271787ab8883f9 0x893d51ec4b563b53 la 4451 verilog code for implementation of des cycloneIII ep2c20 EP2C20-6 PDF

    XIP2018

    Abstract: XC2V50E-7 XCV200E-8
    Contextual Info: AES Encryption Core April 15, 2003 Product Specification AllianceCORE Facts Core Specifics See Table 1 Provided with Core Documentation Product Specification, tests set details Design File Formats EDIF Netlist, or VHDL or Verilog Source RTL available at extra cost


    Original     		1076-Compliant XIP2018 XC2V50E-7 XCV200E-8 PDF

    vhdl code for des decryption

    Abstract: vhdl code for multiplexer 64 to 1 using 8 to 1 Triple Data Encryption Standard Triple DES XC2S100-5
    Contextual Info: MC-XIL-DES Data Encryption Standard Engine Core June 28, 2002 Product Specification AllianceCORE Facts Core Specifics See Table 1 Provided with Core Documentation User’s Guide Design File Format Verilog or VHDL RTL Constraint Files .ucf Verification Testbench


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    verilog code for discrete linear convolution

    Abstract: verilog code for ultrasonic sensor with fpga verilog code for linear convolution by circular c image enhancement verilog code verilog code for linear convolution by circular adc matlab code vhdl code for Circular convolution iir filter butterworth verilog vhdl code of 32bit floating point adder verilog code image processing filtering
    Contextual Info: White Paper Increase Bandwidth in Medical & Industrial Applications With FPGA Co-Processors Introduction Programmable logic devices PLDs have long been used as primary and co-processors in telecommunications (see Building Blocks for Rapid Communication System Development white paper). Digital signal processing (DSP) in


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    verilog code for CORDIC to generate sine wave

    Abstract: verilog code for cordic algorithm vhdl code for cordic vhdl code for rotation cordic CORDIC to generate sine wave fpga verilog code to generate sine wave vhdl code to generate sine wave verilog code for cordic CORDIC to generate sine wave vhdl code for FFT 32 point
    Contextual Info: NCO MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Date: 10.0 July 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other


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    fsk by simulink matlab

    Abstract: VHDL code for CORDIC to generate sine wave VERILOG Digitally Controlled Oscillator vhdl code for cordic algorithm verilog code for cordic algorithm vhdl code to generate sine wave matlab code to generate sine wave using CORDIC verilog code for CORDIC to generate sine wave vhdl code for cordic matlab code for CORDIC to generate sine wave
    Contextual Info: NCO Compiler MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com Core Version: 2.0.1 Document Version: 2.0.1 rev. 1 Document Date: July 2002 Copyright NCO Compiler MegaCore Function User Guide Copyright 2002 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo,


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    VERILOG Digitally Controlled Oscillator

    Abstract: matlab code to generate sine wave using CORDIC verilog code of sine rom verilog code to generate sine wave QFSK EP3C10F256 verilog code for digital modulation cyclone iii matlab code for half adder CORDIC to generate sine wave fpga VHDL code for CORDIC to generate sine wave
    Contextual Info: NCO MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Date: 11.0 May 2011 Copyright 2011 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other


    Original     		PDF

    verilog code for fir filter using DA

    Abstract: implementation of 16-tap fir filter using fpga xilinx code for 8-bit serial adder 4 tap fir filter based on mac vhdl code 16-Tap, 8-Bit FIR Filter Application Guide," Xilinx Publications, design of FIR filter using vhdl abstract vhdl code for distributed arithmetic using systolic arrays 3 tap fir filter based on mac vhdl code verilog code for distributed arithmetic vhdl code for 8-bit serial adder
    Contextual Info: A Guide to Using Field Programmable Gate Arrays FPGAs for Application-Specific Digital Signal Processing Performance Gregory Ray Goslin Digital Signal Processing Program Manager Xilinx, Inc. 2100 Logic Dr. San Jose, CA 95124 Abstract: FPGAs have become a competitive alternative for high performance DSP applications, previously dominated by


    Original     		16-Tap JAN95. XC6200 verilog code for fir filter using DA implementation of 16-tap fir filter using fpga xilinx code for 8-bit serial adder 4 tap fir filter based on mac vhdl code 16-Tap, 8-Bit FIR Filter Application Guide," Xilinx Publications, design of FIR filter using vhdl abstract vhdl code for distributed arithmetic using systolic arrays 3 tap fir filter based on mac vhdl code verilog code for distributed arithmetic vhdl code for 8-bit serial adder PDF

    LTM4062

    Abstract: CORE8051 ADC DAC Verilog 2 bit Implementation AC321
    Contextual Info: Application Note AC321 Using Fusion for Closed-Loop Power Supply Margining Overview A growing number of embedded systems designers want the ability to dynamically alter the precise value of a power supply's voltage. Closed-loop power supply margining is a technique whereby a power rail is


    Original     		AC321 LTM4062 CORE8051 ADC DAC Verilog 2 bit Implementation AC321 PDF

    vhdl code manchester encoder

    Abstract: vhdl code for manchester decoder vhdl code for clock and data recovery manchester verilog decoder manchester encoder manchester code verilog vhdl code for nrz vhdl manchester vhdl manchester encoder manchester encoder xilinx
    Contextual Info: Application Note: CoolRunner CPLDs R XAPP339 v1.2 Jaunary 10, 2001 Manchester Encoder-Decoder for Xilinx CPLDs Summary This application note provides a functional description of VHDL and Verilog source code for a Manchester Encoder Decoder. The reasons to use Manchester code are discussed. The code


    Original     		XAPP339 XC9572 XCR3064XL XAPP339 vhdl code manchester encoder vhdl code for manchester decoder vhdl code for clock and data recovery manchester verilog decoder manchester encoder manchester code verilog vhdl code for nrz vhdl manchester vhdl manchester encoder manchester encoder xilinx PDF

    cyclic redundancy check verilog source

    Abstract: vhdl code manchester encoder vhdl code for manchester decoder vhdl code for clock and data recovery manchester code vhdl manchester verilog code for uart communication manchester manchester verilog decoder vhdl code for uart communication
    Contextual Info: Application Note: CoolRunner CPLDs R XAPP339 v1.3 October 1, 2002 Manchester Encoder-Decoder for Xilinx CPLDs Summary This application note provides a functional description of VHDL and Verilog source code for a Manchester Encoder Decoder. The reasons to use Manchester code are discussed. The code


    Original     		XAPP339 XC9572, XCR3064XL, XC2C64 XAPP339 cyclic redundancy check verilog source vhdl code manchester encoder vhdl code for manchester decoder vhdl code for clock and data recovery manchester code vhdl manchester verilog code for uart communication manchester manchester verilog decoder vhdl code for uart communication PDF

    block diagram baugh-wooley multiplier

    Abstract: baugh-wooley multiplier baugh-wooley multiplier verilog block diagram unsigned baugh-wooley multiplier application diagram baugh-wooley multiplier diagram for 4 bits binary multiplier circuit vhdl 8-bit multiplier VERILOG block diagram of 8*8 array multiplier QL2007 QL2009
    Contextual Info: Back High Performance Multipliers in QuickLogic FPGAs Introduction Performing a hardware multiply is necessary in any system that contains Digital Signal Processing DSP functionality such as filtering, modulation, or video processing. Often there is an off-the-shelf component that the


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    verilog code for dual port ram with axi interface

    Abstract: XC6SLX25T-2CSG324 UG473 verilog code for dual port ram with axi lite interface XC6VLX75T-2FF784 hamming code in vhdl axi wrapper blk_mem_gen verilog code for pseudo random sequence generator in state diagram of AMBA AXI protocol v 1.0
    Contextual Info: LogiCORE IP Block Memory Generator v7.1 DS512 April 24, 2012 Product Specification Introduction LogiCORE IP Facts The Xilinx LogiCORE IP Block Memory Generator BMG core is an advanced memory constructor that generates area and performance-optimized memories


    Original     		DS512 verilog code for dual port ram with axi interface XC6SLX25T-2CSG324 UG473 verilog code for dual port ram with axi lite interface XC6VLX75T-2FF784 hamming code in vhdl axi wrapper blk_mem_gen verilog code for pseudo random sequence generator in state diagram of AMBA AXI protocol v 1.0 PDF

    XC5VLX50-FF676

    Abstract: ramb16bwer SPARTAN 3an spartan 3a vhdl code for 9 bit parity generator DS512 4VLX60 EE core SPARTAN 3an power of 2 vhdl code for 8 bit parity generator
    Contextual Info: Block Memory Generator v2.6 DS512 October 10, 2007 Product Specification Introduction LogiCORE IP Facts The Xilinx LogiCORE IP Block Memory Generator core is an advanced memory constructor that generates area and performance-optimized memories using embedded block RAM resources in Xilinx FPGAs.


    Original     		DS512 XC5VLX50-FF676 ramb16bwer SPARTAN 3an spartan 3a vhdl code for 9 bit parity generator 4VLX60 EE core SPARTAN 3an power of 2 vhdl code for 8 bit parity generator PDF

    AM29LV320

    Abstract: AM29LVxxx 28F160B3 28F640C3 29LV160 AM29LV320D AP-657 INTEL application notes Intel AP A18A18
    Contextual Info: AP-747 APPLICATION NOTE Multi-Source Solution for Intel 28Fxx0C3 Advanced+ Boot Block and AMD* AM29LVxxxx October 2001 NOTE: This document formerly known as Multi-Source Solution for Intel® 28F160B3 Advanced+Boot Block and AMD* 29LV160. Order Number: 292295-001


    Original     		AP-747 28Fxx0C3 AM29LVxxxx 28F160B3 29LV160. 28FxxxC3 48-Lead 29LVxxx 28F800C3, AM29LV320 AM29LVxxx 28F640C3 29LV160 AM29LV320D AP-657 INTEL application notes Intel AP A18A18 PDF

    tcb8000c

    Abstract: tcb8000a LCD Module topway by topway tcb8000c graphic lcd panel fpga example MRI circuit sandisk sd protocol block diagram of mri de2 video image processing altera LCD Module topway datasheet by topway block diagram of mri machine
    Contextual Info: MRI Spinal Segmentation Based on the Nios II Processor First Prize MRI Spinal Segmentation Based on the Nios II Processor Institution: Information Science Institute, College of Computer and Information Technology, Beijing Jiaotong University Participants:


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    RAMB16BWER

    Abstract: vhdl code hamming ecc 8kx1 RAM XC6VLX365T-FF1759-1 Xilinx Virtex6 Design Kit vhdl code hamming DS512 RAMB36 verilog code hamming vhdl spartan 3a
    Contextual Info: Block Memory Generator v3.2 DS512 June 24, 2009 Product Specification Introduction • The Xilinx LogiCORE IP Block Memory Generator core is an advanced memory constructor that generates area and performance-optimized memories using embedded block RAM resources in Xilinx FPGAs.


    Original     		DS512 RAMB16BWER vhdl code hamming ecc 8kx1 RAM XC6VLX365T-FF1759-1 Xilinx Virtex6 Design Kit vhdl code hamming RAMB36 verilog code hamming vhdl spartan 3a PDF

    29LV160

    Abstract: Am29LV800 28F160 28F160B3 28F640B3 AP-657 INTEL application notes Intel AP Am29LV0641D 38000-3FFFF
    Contextual Info: AP-680 AP-680 APPLICATION NOTE Multi-Source Solution for Intel 28Fxx0B3 Advanced Boot Block and AMD* AM29LVxxxx October 2001 NOTE: This document formerly known as Multi-Source Solution for Intel® 28F160B3 Advanced Boot Block and AMD 29LV160. Order Number: 297876-004


    Original     		AP-680 28Fxx0B3 AM29LVxxxx 28F160B3 29LV160. 28FxxxB3 48-Lead 29LVxxx. 29LV160 Am29LV800 28F160 28F640B3 AP-657 INTEL application notes Intel AP Am29LV0641D 38000-3FFFF PDF