ERS 2202 1 Search Results

320VA

Abstract: amecon AMECON 2136
Contextual Info: TRANSFORMERS 5600 0P M E O 1N Tbeßnergy Saver fo r 26 Years 5600 LARGEST SELECTION OF HEAV Y DUTY 5 0 / 6 0 H z . T O R O ID A L POWER T R A N S F O R M E R S . For Line Voltage Apply Input To: Connect 115V 1& 2 1 to 3 and 2 to 4 230V 1& 4 2 to3 BLK - r

Contextual Info: Revised Mar. 1998 JS9P08-AS 1. RF PERFORMANCE SPECIFICATIONS Ta= 25°C CHARACTERISTICS Output Power at ldB Compression Point Power Gain at ldB Compression Point Drain Current Power Added Efficiency SYMBOL CONDITION MIN. TYP. MAX. UNIT 23.0 24.0 — dBm

Contextual Info: A m P A L 2 2 P 1 O B /A L /A Advanced Micro Devices 24-Pin Combinatorial TTL Programmable Array Logic DISTINCTIVE CHARACTERISTICS • As fast as 15 ns maximum propagation delay ■ Universal combinatorial architecture ■ Programmable output polarity ■

BMA16X16

Contextual Info: SI GE C P L E S S E Y MARCH 1997 S E M I C O N D U C T O R S CLA80000 SERIES HIGH DENSITY CMOS GATE ARRAYS INTRODUCTION ARRAY SIZES The CLA80k gate array series from GEC Plessey Semiconductors offers advantages in speed and density over previous array series. Improvements in design combined with

NT 145 AX Thin Film

Contextual Info: ¿mmsuskms SSI 32R2200R/2201R/2202R/2203R +5V, 4-, 6-Channel Thin Film Read/Write Device A TDK G roup/C om pany Advance Information January 1995 DESCRIPTION FEATURES The SS I32R 2200R /2201R /2202R /2203R are BiCMOS m onolithic integrated circuits designed for use w ith

LM2402T

Abstract: lm2402 U12402 023p 2n5770 equivalent LM2202 P6201 CRT MONITOR SCHEMATIC DIAGRAM signal path designer
Contextual Info: Semiconductor LM2402 Monolithic Triple 3 ns CRT Driver • Well m atched w ith LM 2202 video pream ps General Description The LM 2402 is an integrated high voltage C R T driver circuit designed for use in high resolution co lo r m onitor applica­ tions. The IC contains three high input im pedance, w ide

Contextual Info: AT28MC020 Features • • • • • • • • • • • Fast Read Access Time -150 ns Automatic Page Write Operation Internal Address and Data Latches for 128 Bytes Internal Control Timer Fast Write Cycle Time Page Write Cycle Time -1 0 ms maximum 1 to 128 Byte Page Write Operation

ITT 2222 A

Abstract: itt 2222
Contextual Info: Si GEC P L E S S E Y APRIL 1997 S E M I C O N D U C T O R S CLA90000 SERIES HIGH DENSITY CMOS GATE ARRAYS INTRODUCTION BENEFITS The CLA90000 family of gate arrays from GEC Plessey Semiconductors GPS consists of 14 fixed-size arrays with the option of building optimized arrays with up to 1.1 million

Contextual Info: ÖTblTaS QG7b55b M • TIBPAL16L8-30M , TIBPAL16R4-30M , TIBPAL16R6-30M , TIBPAL16R8-30M TIBPAL16L8-25C, TIBPAL16R4-25C, TIBPAL16R6-25C, T IB P A L16R8-25C LOW-POW ER HIGH-PERFORM ANCE IMPACT PAL CIRCUITS 03337, FEBRUARY 1984-REVISED AUGUST 1989 H ig h -P erfo rm an ce O p eration

ir 847p

Abstract: 3010P-K Y744 CNY181V crt5000 2106U T1102G T1103G DT1103 64bcn
Contextual Info: Tem ic S e m i c o n d u c t o r s Optoisolators C haracteristics V io Package Type VRMS CTR V BRCEO Ip = I0 m A IC=1 m A % V @ Ip and Ic V CEsat ton / toff Ic Rl =100 q V mA mA |xs ! mA 6 Pin Optoisolators - with Transistor Output ^ 1 4 N 2 5 2i 3750 100020)

CD 5888 ic

Abstract: CL 2181 ic AE-6410-2 JC102 50920a C501 bb 509 molex 6410 ic la 7688 HC-102
Contextual Info: NO. OF CCTS DIMN. 'A ' 2.54 .100 ( 5.08 .200 ( 7.62 .300 (10.16 .400 (12.70 .500 (15.24 .600 (17.78 .700 (20.32 .800 (22.86 .900 (25.40 1.000 (27.94 1.100 (30.48 1.200 (33.02 1.300 (3 5 5 6 1.400 (38.10 1.500 (40.64 1.600 (43.18 1.700 (45.72 1.800 (48.26

Contextual Info: AT28C010 Com/Ind Features • • • • • • • • • • • Fast Read Access Time -120 ns Automatic Page Write Operation Internal Address and Data Latches for 128 Bytes Internal Control Timer Fast Write Cycle Time Page Write Cycle Time • 10 ms maximum

5AC312

Abstract: P5AC312-25 N5AC312-25 D5AC312-30 D5AC312 d5ac312-25 N5AC P5AC312-30 p5ac312 uchi
Contextual Info: in tJ . 5AC312 1-MICRON CMOS 12-MACROCELL PLD • High-Performance LSI Semi-Custom Logic Alternative for Low-End Gate Arrays, TTL, and 74HC- or 74HCT SSI and MSI Logic, and PLDs ■ High Speed tpp 25 ns, 66 MHz Performance Pipelined, 33.3 MHz w/Feedback ■ Programmable Output Registers

5AC312

Abstract: 290156 D5AC312 D5AC312-30
Contextual Info: in U I, 5AC312 1-MICRON CMOS 12-MACROCELL PLD • High-Performance LSI Semi-Custom Logic Alternative for Low-End Gate Arrays, TTL, and 74HC- or 74HCT SSI and MSI Logic, and PLDs ■ High Speed tpo 25 ns, 66 MHz Performance Pipelined, 33.3 MHz w/Feedback ■ Programmable Output Registers

ib17

Contextual Info: M D M M ! 0 M [F © [s ]ß M ? 0 © M SPECIAL ENVIRONMENT 80960CF-30, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining

Contextual Info: COM’L: -5/7/B/B-2/A, 10/2 MIL: -10/12/15/B/A Advanced Micro Devices PAL20R8 Family 24-Pin TTL Programmable Array Logic DISTINCTIVE CHARACTERISTICS • As fast as 5 ns maximum propagation delay ■ Power-up reset for initialization ■ Popular 24-pin architectures: 20L8,20R8,

Contextual Info: August 1992 LXP2180A Tl ESF Framer/Formatter The LXP2180A is one of a family o f Level One T l interface solutions. It is compatible with the LXT300 series transceiv­ ers and LXP600 series clock adapters. The device interfaces to the D S1 1.544 Mbps digital trunk. A pin compatible dropin replacement for the Dallas DS2180A, the LXP2180A

Contextual Info: in y A28F400BR-T/B 4-MBIT 256K X 16, 512K X 8 SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY Automotive Intel SmartVoltage Technology — 5V or 12V Program/Erase — 5V Read Operation Very High Performance Read — 80 ns Max. Access Time, 40 ns Max. Output Enable T

Contextual Info: Tem ic 29C93A MATRA MHS ECMA102/V110 Terminal Rate Adaptor Circuit TRAC Description The 29C93A is a Terminal Rate Adaptor Circuit (TRAC) performing speed adaptation between synchronous/asynchronous V24 terminals through ISDN 64 kbps “B” channel. The TRAC can be connected to “B” channel using a

TDA 7277

Abstract: TDA 8345 TDA 7988 tda 9580 TDA 8344 TDA 9394 TDA 8659 AN tda 8945 j tda 7840 ic tda 9361
Contextual Info: Tem ic S e m i c o n d u c t o r s Addresses Europe France T E M IC F rance L es Q u a d ra n ts 3. av en u e du centre B.P. 309 7 8 0 5 4 S t.-Q u e n tin -e n -Y v e lin e s C ed ex Tel: 33 1 3 0 6 0 7 0 0 0 Fax: 33 1 3 0 6 0 7111 Germany T E M IC T E L E F U N K E N

FGT 313

Contextual Info: in te i ¡860 XR 64-BIT MICROPROCESSOR • Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction per Clock — Up to Two Floating-Point Results per Clock Compatible with Industry Standards — ANSI/IEEE Standard 754-1985 for

VOGT n4

Abstract: VOGT n3
Contextual Info: aRFLÈMiNAR'. Am79Q4457/5457 AMDB Quad Subscriber Line Audio Processing CircuitNon-Programmable QSLAC -NP Devices TABLE OF CONTENTS Distinctive Characteristics .203

LT1667

Abstract: LT1665 CA10 A058 dk 300 a008 82360SL LCD CMC 116 L01 2164 intel INTEL 82360 CD 2399 GP A049 crystal
Contextual Info: 5bE ]> • 4ÔSbl7S D i n o S M E34 « I T L 1 up/prpHLS irrte* Intel386 CORP SL MICROPROCESSOR SuperSet INTEL 'T~-(4c\ 1 7 -3 ^ Highly-Integrated Static Intel386™ SL Microprocessor Complete ISA Peripheral Subsystem System-Wide Power Management Static lntel386TM SL CPU

Contextual Info: ANALOG DEVICES □ 32/40-Bit IEEE Floating-Point DSP Microprocessor ADSP-21020 FE A T U R E S Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture M axim izes Signal Processing Performance 30 ns, 33.3 M IP S Instruction Rate. Single-Cycle