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    ERROR CORRECTION, VERILOG SOURCE Search Results

    ERROR CORRECTION, VERILOG SOURCE Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    UDS2983R/B
    		Rochester Electronics LLC UDS2983 - High Voltage, High Current Source Driver PDF Buy
    UDS2981R/B
    		Rochester Electronics LLC UDS2981 - High Voltage, High Current Source Driver PDF Buy
    UCC28056BDBVT
    		Texas Instruments 6-pin high performance CRM/DCM PFC controller Visit Texas Instruments Buy
    UCC28056CDBVR
    		Texas Instruments 6-pin high performance CRM/DCM PFC controller Visit Texas Instruments Buy
    UCC28056BDBVR
    		Texas Instruments 6-pin high performance CRM/DCM PFC controller Visit Texas Instruments Buy

    ERROR CORRECTION, VERILOG SOURCE Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    vhdl code REED SOLOMON

    Abstract: verilog code parity error correction, verilog source XILINX vhdl code REED SOLOMON e core encoder verilog coding error correction code in vhdl vhdl code REED SOLOMON xilinx Verilog Block Error Code vhdl code for 8 bit parity generator
    Contextual Info: XF-RSENC Reed Solomon Encoder January 10, 2000 Product Specification AllianceCORE Facts Memec Design Services 7810 South Hardy Drive, Suite 104 Tempe, Arizona 85284 USA Phone: +1 888-845-5585 USA +1 480-753-5585 Fax: +1 480-753-5899 E-mail: info@memecdesign.com


    Original     		4000X, 900Mbps) vhdl code REED SOLOMON verilog code parity error correction, verilog source XILINX vhdl code REED SOLOMON e core encoder verilog coding error correction code in vhdl vhdl code REED SOLOMON xilinx Verilog Block Error Code vhdl code for 8 bit parity generator PDF

    XILINX vhdl code REED SOLOMON

    Abstract: vhdl code REED SOLOMON XILINX vhdl code download REED SOLOMON error correction code in vhdl encoder verilog coding vhdl code for dvb vhdl code download REED SOLOMON vhdl code for 9 bit parity generator error correction, verilog source verilog code for service description table table
    Contextual Info: XF-RSENC Reed Solomon Encoder November 9, 1998 Product Specification AllianceCORE Facts Core Specifics Memec Design Services Maria Aguilar, Project Coordinator 1819 S. Dobson Rd., Suite 203 Mesa, AZ 85202 Phone: +1 888-360-9044 USA +1 602-491-4311 (outside the USA)


    Original     		PDF

    delay locked loop verilog

    Abstract: 100C CLK180 XAPP132 XAPP1
    Contextual Info: APPLICATION NOTE APPLICATION NOTE  XAPP132 October 21, 1998 Version 1.31 Using the Virtex Delay-Locked Loop 13* Advanced Application Note Summary The Virtex FPGA series provides four fully digital dedicated on-chip Delay-Locked Loop (DLL) circuits which provide zero propagation delay, zero clock


    Original     		XAPP132 delay locked loop verilog 100C CLK180 XAPP1 PDF

    VOGT K3

    Abstract: vogt k4
    Contextual Info: 3GPP LTE Turbo Reference Design 3GPP LTE Turbo Reference Design AN-505-2.1 Application Note The Altera 3GPP LTE Turbo Reference Design demonstrates using Turbo codes for encoding with trellis termination support, and forward error correction FEC decoding with early termination support. The reference design is suitable for 3GPP


    Original     		AN-505-2 VOGT K3 vogt k4 PDF

    verilog code for amba apb master

    Abstract: verilog code for apb verilog code for amba apb bus i2s philips synchronous fifo design in verilog verilog code for i2s bus testbench of a transmitter in verilog philips I2S bus specification verilog code for 8 bit fifo register testbench verilog ram asynchronous
    Contextual Info: Meets Philips Inter-IC Sound Bus Specification Supported modes I2S-APB − I2S Philips Inter-IC Sound Bus Core for AMBA APB − Right Justified − Left Justified − DSP Two clock domains − APB the host side clock do- The I2S-APB core integrates eight channels of Inter-IC Sound compatible serial buses.


    Original     		PDF

    I2S bus specification

    Abstract: verilog code for amba apb master verilog code for apb testbench of a transmitter in verilog philips I2S bus specification i2s specification verilog code for amba apb bus testbench verilog ram asynchronous verilog code for digital clock AMBA BUS vhdl code
    Contextual Info:  Meets Philips Inter-IC Sound Bus Specification  Supported modes I2S-APB  I2S Philips Inter-IC Sound Bus Core for AMBA APB  Right Justified  Left Justified  DSP  Two clock domains  APB the host side clock do- The I2S-APB core integrates eight channels of Inter-IC Sound compatible serial buses.


    Original     		PDF

    traffic light controller IN JAVA

    Abstract: vhdl code for traffic light control verilog hdl code for parity generator sdc 2025 altera CORDIC ip error correction code in vhdl interlaken Reed-Solomon Decoder verilog code verilog code for fir filter modelsim 6.3g
    Contextual Info: MegaCore IP Library Release Notes and Errata 101 Innovation Drive San Jose, CA 95134 www.altera.com MegaCore Library Version: 10.0 Document Version: 10.0.2 Document Date: 15 September 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other


    Original     		PDF

    design of scrambler and descrambler

    Abstract: vhdl code scrambler verilog code for implementation of des error correction code in vhdl vhdl code for phase shift Descrambler vhdl code for scrambler descrambler cell phone vhdl code for pseudo random sequence generator crc 16 verilog
    Contextual Info: DSD Distributed Sample Descrambler January 10, 2000 Product Specification AllianceCORE Facts CSELT S.p.A Via G. Reiss Romoli, 274 I-10148 Torino, Italy Phone: +39 011 228 7165 Fax: +39 011 228 7003 E-mail: viplibrary@cselt.it URL: www.cselt.it Features


    Original     		I-10148 53-bit design of scrambler and descrambler vhdl code scrambler verilog code for implementation of des error correction code in vhdl vhdl code for phase shift Descrambler vhdl code for scrambler descrambler cell phone vhdl code for pseudo random sequence generator crc 16 verilog PDF

    Marvell PHY 88E1111 Datasheet

    Abstract: 88E1111 88E1111 PHY registers map 88E1145 Marvell 88E1111 Transceiver Marvell PHY 88E1111 stratix iii Datasheet vhdl code for ddr2 vhdl median filter programming 88E1111 vhdl code for FFT 32 point
    Contextual Info: MegaCore IP Library Release Notes and Errata 101 Innovation Drive San Jose, CA 95134 www.altera.com MegaCore Library Version: Document Version: Document Date: 9.0 9.0.5 1 July 2009 Copyright 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other


    Original     		PDF

    TSMC Flash memory 0.18

    Abstract: 32Gb Nand flash toshiba tsmc 0.18 flash TSMC embedded Flash ahb wrapper vhdl code ahb wrapper verilog code toshiba NAND Flash MLC TSMC Flash interface flash controller verilog code Toshiba MLC flash
    Contextual Info: NANDFLASHCTRL NAND Flash Memory Controller Core Implements a flexible controller for NAND flash memory devices from 2 to 128 Gb single device . A smaller controller for up to 2 Gb devices is also available. The full-featured core efficiently manages the read/write interactions between a master


    Original     		FAT12/16/32 TSMC Flash memory 0.18 32Gb Nand flash toshiba tsmc 0.18 flash TSMC embedded Flash ahb wrapper vhdl code ahb wrapper verilog code toshiba NAND Flash MLC TSMC Flash interface flash controller verilog code Toshiba MLC flash PDF

    vhdl code hamming

    Abstract: vhdl coding for hamming code vhdl code for pipelined matrix multiplication vhdl code for matrix multiplication vhdl code hamming ecc parity ECC SEC-DED Hamming code SRAM verilog code for matrix multiplication SECDED RTAX2000S vhdl code SECDED
    Contextual Info: Application Note AC273 Using EDAC RAM for RadTolerant RTAX-S FPGAs and Axcelerator FPGAs Applies to EDAC Core from Libero IDE v7.1 or Older Introduction Actel's newest designed-for-space Field Programmable Gate Array FPGA family, the RTAX-S, is a highperformance, high-density antifuse-based FPGA with embedded user static RAM (SRAM). Based on Actel's


    Original     		AC273 l011011101101 vhdl code hamming vhdl coding for hamming code vhdl code for pipelined matrix multiplication vhdl code for matrix multiplication vhdl code hamming ecc parity ECC SEC-DED Hamming code SRAM verilog code for matrix multiplication SECDED RTAX2000S vhdl code SECDED PDF

    XILINX vhdl code REED SOLOMON encoder decoder

    Abstract: Reed-Solomon Decoder verilog code verilog code for digital calculator XILINX vhdl code download REED SOLOMON Reed-Solomon Decoder XILINX vhdl code REED SOLOMON 941-740 Solomon vhdl code download REED SOLOMON viterbi convolution
    Contextual Info: Reed-Solomon Decoder January 10, 2000 Product Specification AllianceCORE Facts Integrated Silicon Systems, Ltd. 50 Malone Rd Belfast BT9 5BS Northern Ireland Phone: +44 1232 664664 Fax: +44 1232 669664 E-Mail: info@iss-dsp.com URL: www.iss-dsp.com Features


    Original     		4000X, XILINX vhdl code REED SOLOMON encoder decoder Reed-Solomon Decoder verilog code verilog code for digital calculator XILINX vhdl code download REED SOLOMON Reed-Solomon Decoder XILINX vhdl code REED SOLOMON 941-740 Solomon vhdl code download REED SOLOMON viterbi convolution PDF

    Puncturing vhdl

    Abstract: verilog code for BPSK matched filter hdl codes binary multiplier gf Vhdl code Convolutional Puncturing Pattern convolutional viterbi viterbi algorithm tcl script ModelSim
    Contextual Info: Viterbi Compiler MegaCore Function November 2001 User Guide 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com A-UG-VITERBI-3.0 Viterbi Compiler MegaCore Function User Guide Copyright  2001 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all


    Original     		00e-01 00e-02 00e-03 00e-04 00e-05 00e-06 00e-07 Puncturing vhdl verilog code for BPSK matched filter hdl codes binary multiplier gf Vhdl code Convolutional Puncturing Pattern convolutional viterbi viterbi algorithm tcl script ModelSim PDF

    scaler verilog code

    Abstract: Block Diagram of 8279 vhdl 4-bit binary calculator car Speed Sensor circuit diagram 4 bit microprocessor using vhdl applications of 8279 verilog code for 8 bit fifo register project of 16 bit microprocessor using vhdl Key rollover fifo vhdl xilinx
    Contextual Info: XF8279 Programmable Keyboard Display Interface November 9, 1998 Product Specification AllianceCORE Facts Maria Aguilar, Project Coordinator Memec Design Services 1819 S. Dobson Rd., Suite 203 Mesa, AZ 85202 Phone: +1 888-360-9044 in the USA +1 602-491-4311 (international)


    Original     		XF8279 scaler verilog code Block Diagram of 8279 vhdl 4-bit binary calculator car Speed Sensor circuit diagram 4 bit microprocessor using vhdl applications of 8279 verilog code for 8 bit fifo register project of 16 bit microprocessor using vhdl Key rollover fifo vhdl xilinx PDF

    electronic tutorial circuit books

    Abstract: schematic diagram of TV memory writer different vendors of cpld and fpga grid tie inverter schematics H7B FET PICO base station datasheet 16x4 ram vhdl alu project based on verilog cut template DRAWING fet p60
    Contextual Info: Title Page Cadence Interface/ Tutorial Guide Introduction Getting Started Design Entry Functional Simulation Design Implementation Timing Simulation Design and Simulation Techniques Manual Translation Tutorial Glossary Program Options Processing Designs with


    Original     		XC2064, XC3090, XC4005, XC5210, XC-DS501, figures/x7762 electronic tutorial circuit books schematic diagram of TV memory writer different vendors of cpld and fpga grid tie inverter schematics H7B FET PICO base station datasheet 16x4 ram vhdl alu project based on verilog cut template DRAWING fet p60 PDF

    OTN testbench

    Abstract: CC481 XIP2196 OTU2 framer OC48 STS192 XILINX vhdl code REED SOLOMON encoder decoder vhdl code for bram Generic AIS verilog code for TCM decoder
    Contextual Info: STS192 OTN Framer/Digital Wrapper CC481 July 9, 2002 Product Specification AllianceCORE Facts Provided with Core Documentation User Guide, Design Guide EDIF netlist Design File Formats Constraints File cc481.ucf Testbench, test scripts Verification Tool


    Original     		STS192 CC481) cc481 OTN testbench XIP2196 OTU2 framer OC48 XILINX vhdl code REED SOLOMON encoder decoder vhdl code for bram Generic AIS verilog code for TCM decoder PDF

    X5978

    Abstract: orcad schematic symbols library HP700 HW-130 XC2000 XC3000A XC3100A checking FND
    Contextual Info:  Development Systems Products Overview August 6, 1996 Version 1.1 XACTstep: Accelerating Your Productivity The newest version of the XACT development system, XACTstep, started shipping in the fourth quarter of 1995. XACTstep software features a revolutionary combination of


    Original     		PDF

    fpga vhdl code for crc-32

    Contextual Info: Test Methodology of Error Detection and Recovery using CRC in Altera FPGA Devices AN-539-2.0 Application Note This application note describes how to use the enhanced error detection cyclic redundancy check CRC feature in the Arria II, Stratix III, Stratix IV, Stratix V, and


    Original     		AN-539-2 fpga vhdl code for crc-32 PDF

    RTL 8188

    Abstract: RAMB18SDP xerox 1025 ISERDES Virtex-5 FPGA User Guide UG190 RAMB36 vhdl code hamming ecc RAMB36SDP RAMB18 UG190
    Contextual Info: Virtex-5 FPGA User Guide UG190 v5.3 May 17, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the


    Original     		UG190 SSTL18 RTL 8188 RAMB18SDP xerox 1025 ISERDES Virtex-5 FPGA User Guide UG190 RAMB36 vhdl code hamming ecc RAMB36SDP RAMB18 UG190 PDF

    electronic power generator using transistor projects

    Abstract: verilog code voltage regulator vhdl VHDL code for ADC and DAC SPI with FPGA FPGA based dma controller using vhdl verilog code for DFT XC2V8000 ADC07 usb programmer xilinx free verilog code for parallel flash memory source code verilog for matrix transformation
    Contextual Info: Using ARM Core-based Flash MCUs as a Platform for Custom Systems-on-Chip 16-Feb-06 Peter Bishop, Communications Manager, Atmel Rousset Summary Advances in process technology are making it possible to fabricate systems-on-chip SoCs containing hundreds of millions of transistors operating at gigahertz clock frequencies in a


    Original     		16-Feb-06 electronic power generator using transistor projects verilog code voltage regulator vhdl VHDL code for ADC and DAC SPI with FPGA FPGA based dma controller using vhdl verilog code for DFT XC2V8000 ADC07 usb programmer xilinx free verilog code for parallel flash memory source code verilog for matrix transformation PDF

    vhdl code HAMMING LFSR

    Abstract: DDR3 DIMM 240 pinout EP3SL110F1152 ddr3 ram DDR3 ECC SODIMM Fly-By Topology DDR3 sodimm pcb layout vhdl code hamming ecc ddr2 ram DDR2 sdram pcb layout guidelines vhdl code hamming
    Contextual Info: External Memory Interface Handbook Volume 3: Implementing Altera Memory Interface IP 101 Innovation Drive San Jose, CA 95134 www.altera.com EMI_IP-2.0 Document Version: Document Date: 2.0 July 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other


    Original     		PDF

    74hc395

    Abstract: spice model 74hc14 74HC00 pspice model library atmel U136 7400 nand gate LS7400 MARKING CODE N-CHANNEL MOS FIELD EFFECT TRANSISTOR ABEL Design Manual MARKING CODE reran plus generators design with 74ls00
    Contextual Info: Table of Contents Synario ECS and Board Entry Product Overviews Manual You are here Programmable IC Entry Manual Synario ECS and Board Entry Manual ABEL Design Manual Schematic and Board Tools Manual March 1997 Synario ECS and Board Entry Manual 1 Table of Contents


    Original     		PDF

    CoolRISC 816

    Abstract: verilog code voltage regulator vhdl project of 16 bit microprocessor using vhdl abstract for UART simulation using VHDL Jaquet vhdl code for digital to analog converter Jaquet speed block diagram UART using VHDL vhdl code for march c algorithm "Heat meter"
    Contextual Info: ESPRIT DESIGN CLUSTER Action Task 2.28 DIRECTORATE GENERAL III Industry RTD : Information Technologies Contract n° EP 25213 TARDIS MEthodology for LOw Power ASic design MELOPAS DESIGN STORY December 6th, 2000 This document may be published without any restrictions


    Original     		DATE-2000 CoolRISC 816 verilog code voltage regulator vhdl project of 16 bit microprocessor using vhdl abstract for UART simulation using VHDL Jaquet vhdl code for digital to analog converter Jaquet speed block diagram UART using VHDL vhdl code for march c algorithm "Heat meter" PDF

    viterbi decoder for tcm decoders using verilog

    Abstract: soft 16 QAM modulation matlab code 16 QAM modulation verilog code trellis code modulation 5/6 decoder verilog code for TCM decoder bpsk simulink matlab viterbi decoder for tcm decoders vhdl code for modulation Viterbi Trellis Decoder vhdl code for probability finder
    Contextual Info: Viterbi Compiler User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com MegaCore Version: Document Date: 10.0 July 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other


    Original     		PDF